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Breaking the ISA Barrier in Modern Computing

  • Author(s): Venkat, Ashish
  • Advisor(s): Tullsen, Dean M.
  • et al.
Abstract

In recent years, the computing landscape has witnessed a shift towards hardware specialization in response to the rapid growth and expansion of software, changing market risks, and fundamental technological limitations. However, the largest barrier to full exploitation of heterogeneity has by far been the difficulty of programming for them. There is a pressing need for systems that allow the exploitation of highly heterogeneous platforms without creating additional programmer burden. The goal of this dissertation is to empower the hardware/software interface, specifically the Instruction Set Architecture (ISA) and the runtime system, with diverse capabilities to enable the seamless adoption of heterogeneous hardware, without breaking the traditional models of programming.

Existing heterogeneous designs either constrain CPU cores to feature a single ISA or allow multiple ISAs that assign distinct jobs to distinct cores, or at best statically partition work, resulting in a tight coupling of an application to the underlying ISA. This dissertation challenges the assumption that the single-ISA constraint is necessary, and further enables programs to cross a heretofore forbidden boundary -- the ISA. In particular, this dissertation describes a compiler and runtime strategy for swift and seamless process migration across diverse ISAs, and further showcases results from a massive core architecture optimization process that demonstrates the performance and energy efficiency benefits of multi-ISA heterogeneous architectures. In addition to its performance and energy efficiency benefits, this dissertation also explores and demonstrates the security potential of multi-ISA architectures to thwart several evasive variants of the notorious Return-Oriented Programming (ROP) attack. This dissertation further alleviates the complexity concerns of multi-vendor ISA heterogeneity by studying the effect of introducing composite-ISA heterogeneity into a microarchitecturally heterogeneous system, recreating and in many cases superseding the benefits that arise from multi-ISA heterogeneity, essentially with a single ISA.

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