UC San Diego

As technology scales, signals may reach proportionally less and less chip area within a single clock cycle, resulting in multi-cycle paths. One solution is to pipeline such signals, being mindful of pipeline throughput. However, pipeline structures can consume substantial energy. The problem is finding the optimal tradeoff between energy and throughput in determining pipeline architecture. We derive a set of pipeline performance metrics, discover that the optimal energy/ throughput tradeoff is determined by the pipeline depth, and obtain that depth as technology scales