Design and Analysis of Digitally Modulated Transmitters for Efficiency Enhancement
- Author(s): YE, LU
- Advisor(s): NIKNEJAD, ALI M
- et al.
The last decade has witnessed a tremendous growth in wireless communications. Consumer demands for battery-operated mobile devices with versatile, high data-rate communication capabilities that are of low cost, small form-factor and long operating cycle have motivated the research on fully-integrated, back-off-efficient and coexistence-friendly wireless transceivers in CMOS VLSI technology. However, the full integration of an efficient CMOS power amplifier (PA) into such a transceiver is still among the most difficult challenges towards a true System-On-Chip (SOC) solution. This thesis investigates the PA efficiency enhancement techniques for a complete power transmitter system that is fully-integrated and coexistable. Direct digitally modulated transmitter architecture has been identified as one of the most promising solutions to the above challenges. Within such a transmitter, the PA efficiency is able to back off from a high peak efficiency at least with class-B characteristic; meanwhile, the transmit linearity can be more easily improved by digital predistortion due to the direct digital modulation scheme. To validate such a promising architecture, we have built a fully-integrated CMOS digital power transmitter for the IEEE 802.11g 54Mbps application. System-level considerations and design choices are presented with an aim for low out-of-band noise and good transmit linearity. As the core of the transmitter, the RF switching PA is designed for high efficiency with minimum number of on-chip passives that only exercise an accurate control over fundamental and second-harmonic terminations. The class-B efficiency back-off characteristic is further improved by a dynamic impedance modulator which boosts the PA drain impedance at a low instantaneous envelope level. Open-loop phase interpolator based topology is used for the polar phase modulator, which achieves wideband phase modulation with competitive power consumption. Digital baseband filtering is fully optimized at both the algorithm and the hardware level, which offers larger than 60dB attenuation on the close-in spectral images with reduced filter complexity. The prototype has been implemented in a 65nm bulk CMOS technology and has demonstrated a combination of good output power, overall efficiency and spectral purity with a very high level of system integration.