UCLA

Driven by Moore’s law, semiconductor chips have become faster, denser and cheaper through aggressive dimension scaling. The continued scaling not only led to dramatic performance improvements in digital logic applications but also in mixed-mode and/or communication applications. Moreover, size/weight/power (SWAP) restrictions on all high-performance system components have resulted in multi-functional integration of multiple integrated circuits (ICs)/dies in 3D packages/ICs by various system-level approaches. However, these approaches still possess shortcomings and in order to truly benefit from the most advanced digital technologies, the future high-speed/high power devices for communication applications need to be fully integrated into a single CMOS chip. Due to limitations in Si device performance in high-frequency/power applications as well as expensive III-V compound semiconductor devices with low integration density, heterogeneous integration of compound semiconductor materials/devices with Si CMOS platform has emerged as a viable solution to low-cost high-performance ICs.

In this study, we first discuss on channel and drain engineering approaches in the state-of-the-art multiple-gate field-effect transistor to integrate III-V compound semiconductor materials with Si CMOS for improved device performance in mixed-mode and/or communication applications. Then, growth, characterization and electrical analysis on small-area (diameter < 100nm) complete selective-area epitaxy of GaAs/GaN will be demonstrated for achieving ‘dislocation-free’ III-V compound semiconductor film on a Si(001) substrate. Based on a success in dislocation-free heterogeneous III-V film growth, we propose a novel ultra-scaled ‘junction-level’ heterogeneous integration onto mainstream Si CMOS platform. Device architecture and its key features to overcome aforementioned challenges will be given to demonstrate the potential to improve the overall system performance with diverse functionality.