UC San Diego
Low Power CMOS Circuit Techniques for Optical Interconnects and High Speed Pulse Compression Radar
- Author(s): Li, Jun
- Advisor(s): Buckwalter, James F
- et al.
High performance computing and high resolution range sensor motivates the intelligent system innovations such as smart car, smart home/community and 3D motion games. Most importantly, 3D graphics technique requires high performance computation to provide high quality and vivid real-time videos. Accurate motion sensing requires high resolution radar sensor. However, in general, data transmission limits the large scale computation while high resolution radar signal processor limits the detection accuracy. Therefore, low power design for high speed data transmission and high resolution radar signal processor are desired.
Energy efficient transceivers have been aggressively demanded by high performance computing applications. Recently, data center has reached TB/s in 2015 and it would reach 20 TB/s in a few years. Therefore, low cost short range interconnects becomes one of the major limitations for high speed data transmission especially for processor-to-processor and processor-to-memory. Silicon photonics (SiP) has attracted great attentions for its low energy efficiency and less IO pins. In air interface, 15 cm sensing resolution and Gb/s data communication dual mode system enables a layer of network intelligence.
The first portion of the dissertation discusses the energy efficient transceiver
design for optical interconnects. A monolithic micro-ring modulator based transmitter is presented in 130 nm CMOS SOI. In this process, the data rate limitation of monolithic integration is on the eletrical driver. With optimized micro-ring modulator, the transmitter demonstrates 25 Gb/s data rate without pre-emphasis.
Secondly, the scaling trends from FD-SOI CMOS to FinFET process is discussed. Since the monolithic integration can not scale the energy efficiency as hybrid integration due to the limitation of optical devices development, hybrid integration keeps the energy efficiency scaling on behalf of the high fT device in advanced process. An optical and electrical co-design algorithm for the WDM link is proposed which focus on the energy efficiency optimization in hybrid integration. Link budget is analyzed and transceivers with planar 28 nm FD-SOI CMOS and 3D 14 nm FinFET are presented.
Thirdly, a high speed pulse compression radar (PCR) signal processor is presented in 90 nm CMOS. High speed analog correlation is proposed to replace the conventional digital correlation. This relaxes the high speed requirement in analog-to-digital converter (ADC) design. An analog correlation signal processor is implemented with a variable gain amplifier (VGA), a correlator, a delay-lock loop (DLL), a 4-bits DAC and a 4-bits ADC. Additionally, a new closed-loop calibration algorithm is proposed for DC offset and time misalignment.
Finally, a dual mode bidirectional pulse compression radar is proposed. The
radar signal processor is demonstrated in 90 nm CMOS. The system allows 3 Gb/s data transmission in passthrough mode and 10 cm range resolution in radar mode. This is the first demonstration of pulse compression radar signal processor with the features of wireless data communication and high resolution range sensing.