UC Berkeley

Continued increase in the process variability is perceived to be a major roadblock for future technology scaling. Its impact is particularly pronounced in large memory arrays due to both the utilization of minimum sized transistors and their extremely large data capacity. In order to enable the continued scaling of the next-generation embedded SRAM, the ability to monitor and characterize, on-chip, the variations in SRAM functionality and performance becomes critical for both gaining a deeper understanding of the sources of variability and for developing more robust circuits and topologies. This work presents a methodology to characterize, directly, the impact of process variability on the functionality of large SRAM-based cache memories - capable of collecting massive silicon data at little hardware and/or design overhead. In addition, a thorough investigation of various SRAM read stability and writeability metrics, including the proposed large-scale design metrics, is conducted to further understand the utility of each metric for SRAM yield prediction. The large-scale characterization methodology is validated on two different test chips, fabricated in an early commercial low-power 45nm CMOS process. This method can be easily extended to capture more than 6 standard deviations of parameter variations by increasing the SRAM array size, and therefore can serve as a valuable addition to the next-generation SRAM development vehicle.

The enablement of future SRAM scaling will require technology and circuit co-design. The FinFET technology is particularly attractive for nanoscale SRAM design not only for its reduced σ_VTH and better control of the short channel effects (SCE), but also for the architectural flexibility enabled by its unique independently-gated (IG) operation. New bitcell designs are presented to take advantage of this IG operation in the form of a dynamic pass-gate feedback (PGFB). It is shown that the IG FinFET design using dynamic PGFB can both dramatically enhance the read stability of a 6-T SRAM cell and enable the practical design of a 4-T SRAM cell. While increased variability presents a formidable challenge for future SRAM scaling, the presented methodologies, both in testing and design, can facilitate its continuation.