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Statistical based Piecewise Linear Calibration of Nonlinearity in SAR-ADC


In recent years, Successive Approximation Register Analog-to-Digital Converter (SAR-ADC) has received significant attention due to its well-known energy and hardware efficiency, which also benefits even more from technology scaling. Traditionally, designers have to pay extra attention to matching of the elements in the Digital-to-Analog Converter (DAC), commonly capacitors, as the heart of the ADC. In many cases this leads to overdesigning the DAC hence, directly and indirectly, wasting precious area and power efficiency.

In this research we have been seeking for a robust, hardware/energy efficient, non-invasive, and non-interrupting calibration scheme for SAR-ADC. Unlike current state of the art, proposed calibration does not require stringent assumption on layout considerations and it does not affect the throughput of the data. The prototype of the calibration has been implemented on a 12-bit SAR-ADC fabricated in 65 nm CMOS. Measurement results show more than 9 dB improvement in SNDR (from 58 dB without calibration to 67.2 with calibration) and about 19 dB enhancement in SFDR of the ADC (from 62.6 dB without calibration to 81.2 with calibration). In order to demonstrate effectiveness of the proposed calibration in a practical scenario with wide bandwidth input signals, the performance of the ADC is also tested for quantizing the samples of a 256-QAM signal. Measurement results show improvement of EVM of the output from about 42 dB without calibration to 50 dB with calibration.

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