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Open Access Publications from the University of California

VIPER : a 25-MHz, 100-MIPS peak VLIW micro-processor

  • Author(s): Gray, J.
  • Naylor, A.
  • Abnous, A.
  • Bagherzadeh, N.
  • et al.

This paper describes the design and implementation of a very long instruction word (VLIW) microprocessor. The VIPER (VLIW integer processor) contains four pipelined functional units, and can achieve 100 MIPS peak performance at 25 MHz. The procesor is capable of performing multiway branch operations, two load/store operations and up to four ALU operations in each clock cycle, with full register file access to each functional unit. VIPER is the first VLIW microprocessor known that can achieve this level of performance. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 µm technology.

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