Work in NanoCAD targets equivalent scaling improvements - perhaps as much as one full technology generation by establishing new synergies between various silos of application, architecture, design and manufacturing.
With increase in transistor packing density and use ofuni-directional metal routing, resources on local metal layers areincreasingly limited. A major contributor to routing congestion is theminimum metal area (minArea) design rule, which has been steadilyincreasing over the past few technology nodes. For a net which crossesmultiple metal layers (e.g., M2 to M4), polygons on intermediate layers(e.g., M3) i.e. via landing pads must satisfy the minArea rule; thiscreates unnecessary routing blockage, which can lead to area overhead.In this work, we investigated the benefits of introduction into theBEOL stack of a new “supervia” structure, namely, a double-height viaspanning two metal layers without a landing pad on an intermediatemetal layer. We study the benefit of supervia using (i) routing clip-basedevaluation using an optimal ILP-based router (OptRouterSV) and (ii)chip-level evaluation using a commercial routing tool in conjunctionwith MILP-based supervia aware legalization. With the latter, if thelegalization approach fails, the failures are localized to clips, whichare then routed optimally using OptRouterSV. Our results suggest thatwhen the P&R tool is allowed to generate via structures which optimizesfor minArea in stacked vias, using supervia can save∼2% of the chiparea whereas in absence of this option, supervia can save as much as20% of the chip area.
