The Discrete Cosine IVansform (DCT) is used in the MPEG and JPEG compression standards. Thus, the DCT component has stringent timing requirements. The high performance which is required cannot be achieved by a sequential implementation of the algorithm. In this report, we explore different optimization techniques to improve the performance of the DCT. We discuss various pipelining options to further reduce the latency. We present a transformation of the algorithm that reduces the memory requirements and hence, reduces the cost of the implementation. We also describe RT-level implementations of the sequential, pipelined and memory optimized designs.

In this report, we discuss the various issues and problems associated with ASIC reuse. We describe the different models of communication between components and the essential issues in interfacing ASICs that use different communication protocols. We come up with guidelines that help in modeling for reuse. We also propose a new HDL, SpecC, that has the desirable characteristics for co-designing systems. This language is suited for ASIC reuse and overcomes the limitations of VHDL.

In this report, we describe the specify-explore-refine (SER) co-design methodology for design of embedded systems. We describe the necessary design steps in order to map an abstract specification of the system to the final implementation model. We propose a co-design tool based on our co-design methodology. We also present a graphical user interface for the proposed co-design tool.