Objective: The primary objective of this study is to investigate the performance of augmented reality (AR) in representing and displaying 3D holographic models derived from 3D MR acquisitions. In addition, the existing picture archiving and communication system (PACS) will be examined as well.

Methods: A compatible phantom model for the 3.0T standard bore GE MRI scanner was used and fiducial markers set at various known distances were placed on the surface of the model. The distances were measured using a digital caliper, establishing the reference gold standard. Five separate configurations were created using the same phantom model by rearranging the fiducial markers. A set of six total measurements between fiducial markers were made in each configuration: two along the x-direction, two along the y-direction, and two along the z-direction. Four different 3D MR sequences were implemented to scan each configuration. The resulting 3D MR images of each sequence for every configuration were stored as digital imaging and communications in medicine (DICOM) files and sent to PACS. The corresponding six distances were then measured using the built-in PACS ruler tool. Open-source 3D rendering software programs were used to translate the DICOM files into 3D models, which were then loaded onto an AR platform. The 3D models were displayed as holograms and the overlaid distances between the fiducial markers were measured using a physical digital caliper. Since the assumptions for parametric statistical analysis were violated, the nonparametric statistical method was adopted to examine the statistical differences among the three groups (gold standard, PACS, and AR).

Results: The results showed no statistically significant difference between AR measurements and gold standard measurements (p = 0.6208). However, a statistically significant difference between PACS measurements and gold standard measurements (p = 0.0118) was present.

Conclusion: Distance measurements in AR models derived from MRI scans show no statistically significant difference compared to gold standard measurements. AR can be used to accurately measure distance for surgical planning and clinical use.

In this thesis, an oscillator-based touch sensor system is presented. Existing technologies for touchscreen sensors include resistive, capacitive, infrared, and optical imaging; however, none of them is suited for remote sensing in mobile applications. The goal of this thesis is to explore the implementation of a remote sensor system targeted for mobile applications.

The proposed design uses an input-loaded oscillator that senses the ambient capacitance. The variation in ambient capacitance alters the operating frequency of the oscillator. A digital processing unit analyzes the change in frequency, and makes detection based on certain threshold.

The design is achieved by 65nm technology, having a core area of 335um x 230um, power consumption of 2.5mW, and runs on a clock frequency of 16MHz. The system's sensitivity is one order of magnitude higher than current touchscreen technologies, requiring a minimum ambient capacitance variation of 50fF.

Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented.

Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to TDCs in the past that concentrate on the arrival time difference between the divider feedback edge and the reference signal edge. Our approach extracts the timing information that is embedded in voltage domain. This approach not only achieves a higher time resolution, lower phase noise, but also consumes less power. A digital background calibration circuit is also presented to reduce the output spurious tones when the digital PLL operates under fractional-N divisions.

Ring Oscillators (ROs) have the advantage of small area, wide tuning range, and multiphase output. However, their higher phase noise and higher sensitivity to supply noise may seriously deteriorate the wanted signal in wireless receivers. To circumvent this non-ideality, a low overhead phase noise cancellation technique for ring oscillator-based quadrature receivers is presented. The proposed technique operates in background and extracts ring oscillator phase noise as well as supply-induced phase noise from the digital PLL. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain.

In recent years, the unsilenced band at 57~64 GHz frequency range has motivated the building of high-data rate radio systems targeting wireless personal area network (WPAN) applications. To address this demand, a low-noise wide-band integer-N PLL is presented which serves as the carrier generator of a 60 GHz heterogeneous transceiver. The PLL employs sub-sampling phase detection technique to achieve low-noise performance, and provides 48 GHz LO and 12 GHz IF carrier signals for the heterogeneous transceiver.

In this thesis, a SoC (system on chip) solution is proposed for the IF (intermediate frequency) band signal processing and transmission of a radiometer system. This highly integrated and low-power solution is designed for systems where low ADC resolution (< 2-bit) is needed but high-speed data transmission (> 10Gbps) and low-power operation (< 10mW/channel) is strongly desired.

The presented solution includes an array of 2-bit ADCs with duty cycle controlled AGC (automatic gain control) function and a low-power 32:1 serializer. AGC function is included in the front end in order to cope with the wide range of input power (-10dBm ~ -20dBm). The AGC loop is controlled by digitized output duty cycle with an error of 2%. A current steering 5-level tree architecture serializer is designed to achieve a high serializing factor and low-power operation.

The circuit is designed using a 45nm SOI CMOS technology. It is capable of digitizing the IF signals using a power of 5.4mW/channel and transmitting the signals at 32Gbps. The serializer has an output reflection (S22) of less than -10dB from DC to 32GHz with 400mV differential output swing. The serializer consumes less than 50mW of power (3.2mW/channel), and the AGC loop consumes 2.2mW/channel.

An oscillator-based self-capacitance sensing front end system is designed for the commercial grade projected capacitive touch panel. The self-capacitance architecture has potential in terms of 3D extended-range sensing in the vertical (Z) direction however planar resolution (X and Y directions) resolution had to be compromised if it were directly applied to the panel, which is designed for change-transfer based sensors. Incorporating the technique of bootstrapping to null the coupling capacitance between sensing channels, planar resolution can be restored and better Z direction range can be achieved. The design is realized in 65nm and has submitted to TSMC for fabrication.

The groundbreaking idea of public key cryptography and the rapid expansion of the internet

in the 80s opened a new research area for finite field arithmetic. The large size of fields in

cryptography demands new algorithms for efficient arithmetic and new metrics for estimating

finite field operation performance. The area, power, and timing constraints on hand-held

and embedded devices necessitate accurate models to achieve expected goals. Additionally,

cryptosystems need to protect their secrets and hide their internal operation states against

side-channel attacks. Fault-injection attacks or random errors reduce the security of a cryptosystem

and can help a cryptanalyst to extract a system's secrets.

This dissertation covers various aspects of finite field arithmetic to provide predictable,

efficient, and secure elements for cryptography. We provide architecture for an elliptic curve

processor (ECP), which is essentially a finite field processor. We also provide finite field

multipliers over polynomial and optimal normal bases for pipeline and parallel architectures.

To further analyze the behavior of finite field multipliers, we formalize timing, area, and

energy consumption over binary extension fields. To ensure robustness of the multiplication

operation, we provide concurrent error detection (CED) schemes for polynomial and normal

base multipliers and provide the probability of error detection.