Computer architectures are becoming more and more complicated to meet the continuously

increasing demand on performance, security and sustainability from applications. Many factors

exist in the design and engineering space of various components and policies in the architectures,

and it is not intuitive how these factors interact with each other and how they make impacts

on the architecture behaviors. Seeking for the best architectures for specific applications

and requirements automatically is even more challenging. Meanwhile, the architecture design

need to deal with more and more non-determinism from lower level technologies. Emerging

technologies exhibit statistical properties inherently, such as the wearout phenomenon in

NEMs, PCM, ReRAM, etc. Due to the manufacturing and processing variations, there also

exists variability among different devices or within the same device (e.g. different cells on

the same memory chip). Hence, to better understand and control the architecture behaviors,

we introduce the statistical perspective of architecture design: by specifying the architectural

design goals and the desired statistical properties, we guide the architecture design with these

statistical properties and exploit a series of techniques to achieve these properties.

In the first part of the thesis, we introduce Herniated Hash Tables. Our architectural design

goal is that the hash table implementation is highly scalable in both storage efficiency and

performance, while the desired statistical property is to achieve as good storage efficiency

and performance as with uniform distributions given non-uniform distributions across hash

buckets. Herniated Hash Tables exploit multi-level phase change memory (PCM) to in-place

expand storage for each hash bucket to accommodate asymmetrically chained entries. The

organization, coupled with an addressing and prefetching scheme, also improves performance

significantly by creating more memory parallelism.

In the second part of the thesis, we introduce Lemonade from Lemons, harnessing device

wearout to create limited-use security architectures. The architectural design goal is to

create hardware security architectures that resist attacks by statistically enforcing an upper

bound on hardware uses, and consequently attacks. The desired statistical property is that the

system-level minimum and maximum uses can be guaranteed with high probabilities despite of

device-level variability. We introduce techniques for architecturally controlling these bounds

and explore the cost in area, energy and latency of using these techniques to achieve systemlevel

usage targets given device-level wearout distributions.

In the third part of the thesis, we demonstrate Memory Cocktail Therapy: A General,

Learning-Based Framework to Optimize Dynamic Tradeoffs in NVMs. Limited write endurance

and long latencies remain the primary challenges of building practical memory systems from

NVMs. Researchers have proposed a variety of architectural techniques to achieve different

tradeoffs between lifetime, performance and energy efficiency; however, no individual technique

can satisfy requirements for all applications and different objectives. Our architectural

design goal is that NVM systems can achieve optimal tradeoffs for specific applications and

objectives, and the statistical goal is that the selected NVM configuration is nearly optimal.

Memory Cocktail Therapy uses machine learning techniques to model the architecture behaviors

in terms of all the configurable parameters based on a small number of sample configurations.

Then, it selects the optimal configuration according to user-defined objectives which

leads to the desired tradeoff between performance, lifetime and energy efficiency.

Quantum computing promises to speed up scientific and computationally intensive operations. However, the power of quantum computing is limited by the relatively small window of time where the quantum state and be maintained (coherent). To achieve maximum efficiency, not merely to keep this state coherent but to increase computational productivity, maximizing the parallelism of the system is important. The architectural model that is explored here attempts to exploit the relatively small number of operations that are actually performed within a quantum computer to maximize fine-grained, data level parallelism, as opposed to the more common coarse-grained, task level parallelism. This model represents a Multi-SIMD processor design, where multiple SIMD cores are used to boost data level parallelism, but allows for limited task indepence.

The purpose of this work is to explore the effectiveness of parallel processing in a Multi-SIMD quantum architecture. It examines the ability to speedup computation using a combination of parallel processing scheduling and communication awareness, showing up to 7.8X speedup. This information is then used to extract theoretical requirements for bandwidth (>8000 qubits/cycle peak) and throughput (3 qubits/cycle sustained). This research leverages the ScaffCC compiler toolchain [26], which provides a logical-level (i.e., implicitly error-corrected) quantum assembly output as the input to be scheduled and analyzed.

In virtualized environments, typically cloud computing environments, multiple virtual machines run on the same physical host. These virtual machines usually run the same operating systems and applications. This results in a lot of duplicate data blocks in memory. Memory deduplication is a memory optimization technique that attempts to remove this redundancy by storing one copy of these duplicate blocks in the machine memory which in turn results in a better utilization of the available memory capacity.

In this dissertation, we characterize the nature of memory pages that contribute to memory deduplication techniques. We show how such characterization can give useful insights towards better design and implementation of software and hardware-assisted memory deduplication systems. In addition, we also quantify the performance impact of different memory deduplication techniques and show that even though memory deduplication allows for a better cache hierarchy performance, there is a performance overhead associated with copy-on-write exceptions that is associated with diverging pages.

We propose a generic prediction framework that is capable of predicting the stability of memory pages based on the page flags available through the Linux kernel. We evaluate the proposed prediction framework and then discuss various applications that can benefit from it, specifically memory deduplication and live migration.