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Compiler Estimation of Parallelism and Communication for Quantum Computation

  • Author(s): Heckey, Jeff;
  • Advisor(s): Chong, Frederic T;
  • et al.
Abstract

Quantum computing promises to speed up scientific and computationally intensive operations. However, the power of quantum computing is limited by the relatively small window of time where the quantum state and be maintained (coherent). To achieve maximum efficiency, not merely to keep this state coherent but to increase computational productivity, maximizing the parallelism of the system is important. The architectural model that is explored here attempts to exploit the relatively small number of operations that are actually performed within a quantum computer to maximize fine-grained, data level parallelism, as opposed to the more common coarse-grained, task level parallelism. This model represents a Multi-SIMD processor design, where multiple SIMD cores are used to boost data level parallelism, but allows for limited task indepence.

The purpose of this work is to explore the effectiveness of parallel processing in a Multi-SIMD quantum architecture. It examines the ability to speedup computation using a combination of parallel processing scheduling and communication awareness, showing up to 7.8X speedup. This information is then used to extract theoretical requirements for bandwidth (>8000 qubits/cycle peak) and throughput (3 qubits/cycle sustained). This research leverages the ScaffCC compiler toolchain [26], which provides a logical-level (i.e., implicitly error-corrected) quantum assembly output as the input to be scheduled and analyzed.

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