Continuous flow-based microfluidic devices have seen a huge increase in interest because of their ability to automate and miniaturize biochemistry and biological processes, as well as their promise of creating a programmable platform for chemical and biological experimentation. The major hurdle in the adoption of these types of devices is in the design, which is largely done by hand using tools such as AutoCAD or SolidWorks, which require immense domain knowledge and are hard to scale. This paper investigates the problem of automated physical design for continuous flow-based microfluidic very large scale integration (mVLSI) biochips, starting from a netlist specification of the flow layer. After an initial planar graph embedding, vertices in the netlist are expanded into two-dimensional components, followed by fluid channel routing. A new heuristic, DIagonal Component Expansion (DICE) is introduced for the component expansion step. Compared to a baseline expansion method, DICE improves area utilization by a factor of 8.90x and reduces average fluid routing channel length by 47.4%.

Continuous-flow microfluidic devices based on integrated channel networks are becoming increasingly prevalent in research in the biological sciences. At present, these devices are physically laid out by hand by domain experts who understand both the underlying technology and the biological functions that will execute on fabricated devices. The lack of a design science that is specific to microfluidic technology creates a substantial barrier to entry. To address this concern, this article introduces Directed Placement, a physical design algorithm that leverages the natural "directedness" in most modern microfluidic designs: fluid enters at designated inputs, flows through a linear or tree-based network of channels and fluidic components, and exits the device at dedicated outputs. Directed placement creates physical layouts that share many principle similarities to those created by domain experts. Directed placement allows components to be placed closer to their neighbors compared to existing layout algorithms based on planar graph embedding or simulated annealing, leading to an average reduction in laid-out fluid channel length of 91% while improving area utilization by 8% on average. Directed placement is compatible with both passive and active microfluidic devices and is compatible with a variety of mainstream manufacturing technologies.

This paper describes an integrated design, verification, and simulation environment for programmable microfluidic devices called laboratories-on-chip (LoCs). Today's LoCs are architected and laid out by hand, which is time-consuming, tedious, and error-prone. To increase designer productivity, this paper introduces a Microfluidic Hardware Design Language (MHDL) for LoC specification, along with software tools to assist LoC designers verify the correctness of their specifications and estimate their performance. © 2013 IEEE.

A software toolchain for physical design and layout for the flow layer of microfluidic laboratories on a chip ( LoCs) based on integrated microvalve technology is reported. LoCs based on monolithic membrane valves are built using two glass plates that sandwich a thin layer of polydimethylsiloxane (PDMS), a flexible and inert organic polymer. Etched channels in the two glass plates, respectively, provide distinct layers for fluid and pneumatic control. The biochemical reaction executes on the flow layer, while the control layer delivers pressure to each microvalve to control fluids in the flow layer. The planar layout for the fluid flow layer is converted to a scalable vector graphic (SVG) file, which can be used to create a mask that produces patterns for etched channels in one of the two glass layers. If a legal placement and routing solution is not found at N hops, then we try again at N=2 hops, etc. This ensures that a legal placement and routing solution is found for each perimeter component after O(log N) routing attempts. It is clear from a straightforward visual inspection that numerous local perturbations to the component layout could reduce chip area and/or fluid routing channel length.

Seam carving is an algorithm that analyzes image content and can be used for size reduction in a manner that avoids direct compression or downscaling. Seam carving iteratively identifies horizontal and/or vertical paths of least visual importance and removes them from the image; each path removal reduces the length or width of the image by one row or column of pixels. This article adapts seam carving to reduce excess area of flow-based microfluidic chips that have been drawn by hand or by computer-aided heuristics without negatively impacting their functionality. The proposed approach leverages domain knowledge, wherein the image to be carved consists of I/O ports, components, and fluid channels, with known and understood fluidic behavior. Three different variants of seam carving are presented: 1) linear; 2) nonlinear; and 3) nonrectilinear; experimental results show that nonrectilinear, which is the most general of the three, yields the best results: it improves area utilization by 8.6\times and reduces fluid routing channel length by 73% across a set of benchmark microfluidic designs.

This paper introduces a technique based on seam carving to reduce the area of microuidic very large scale integration (mVLSI) chips. Seam carving repeatedly identifies small slices of the device that can be safely removed (carved) and patched without adversely affecting device functionality. Using non-linear seam carving we achieve an average improvement of 4:28x in area utilization and an average reduction in uid routing channel length of 53%.