This report describes the current status of benchmarks for the 1992 High-Level Synthesis Workshop and suggests guidelines for benchmark submission. The benchmark set currently has 9 designs, where each benchmark includes a VHDL description of the design, documentation of the design's functionality, as well as a set of test vectors and expected outputs for simulation. Documentation of the testing strategy the test vectors are also provided with each benchmark. Although the benchmarks are currently written in VHDL, we have attempetd to organize the benchmarks in a language-independent format so that users can easily translate the benchmarks into their favorite HDL; the representative set of test vectors and expected outputs allow a user to ensure, with some level of confidence, that their HDL descriptions preserve the original behavior of the benchmarks. The current benchmark set contains designs that exercise different types of functionality (e.g., DSP, FSM-based, arithmetic, etc.), as well as different types of HDL behavioral constructs (e.g., nested loops and nested conditionals). We conclude with a suggested set of guidelines for benchmark submission.

This report describes an implementation of a scheduling algorithm constructed to use the functionality of existing RT datapath components more effectively. Scheduling algorithms for High-Level Synthesis (HLS) have been based on assumptions that failed to recognize that RT datapath components may have complex, concurrent functionality. The algorithm described in this report takes advantage of a representation that was designed to capture the complex, concurrent functionality of combinatorial RT functional units. This enables the algorithm to utilize RT functions that have been available in existing RT components but had been ignored by other scheduling techniques. The algorithm has been implemented to work with the Interactive Synthesis Environment (ISE).

Traditionally, high-level synthesis (HLS) has been a fully automatic process over which the user has had little or no control. To make HLS an acceptable methodology for expert designers, we need to allow for more interactivity during synthesis. Since the scheduling step in HLS often determines the scope and quality of the ensuing synthesis tasks, we describe behavior-preserving transformations for manual rescheduling of behavior. We present the Structured Finite State Machine (SFSM) design model for scheduled behavior, show its equivalence to the behavioral Control-Data Flow Graph (CDFG), define primitive behavior-preserving transformations and indicate the utility of these transformations. The manual rescheduling capability we describe allows expert designers to alter an automatically generated schedule to overcome simplifications and assumptions made by automatic scheduling algorithms.

The availability of mobile Internet and health devices is enabling new opportunities for health researchers to access an immense amount of digital health data ubiquitously and deliver intervention and treatment online and in real time. However, to take advantage of these opportunities, the researchers need to build systems and applications to collect these data, process them, and deliver actionable items accordingly, which requires building a mobile health (mHealth) system. mHealth solutions are tools designed to assist researchers in creating their desired mHealth systems, but these solutions often have limitations in their setup time, cost, or customization level. This dissertaiton presents ZotCare, a service platform that aims to resolve these limitations by offering ready-to-use mHealth solutions in a shared environment to reduce the cost and provide a service orchestration that can be customized to different types of study by providing tools for personalization and adaptation. ZotCare's contribution also extends to its methods in creating a data pipeline scalable to the number of users, amount of occupied storage, and the load of different types of tasks by considering the opportunities and limitations in mHealth research. This dissertation will provide an introduction and background on mHealth solutions and ZotCare's position. Then, ZotCare's service orchestration is explained to demonstrate its capabilities in creating a customizable environment. This will be followed by ZotCare's data pipeline design challenges to indicate how ZotCare can run mHealth studies at scale. In the end, to showcase ZotCare's practical contribution, several use cases of ZotCare in mHealth research will be provided, followed by a short discussion on other contributions, artifacts, and future work.

This dissertation examined the social psychological processes through which women in rural Nicaragua resist exclusion and seek to create equitable change in their communities. Specifically, using mixed methods analyses, I assessed if women’s involvement in a grassroots feminist organization in rural Nicaragua was associated with individual empowerment and, in turn, women’s efforts to transform their communities with the aim of promoting justice and equality. Data collected and analyzed for this research were 298 quantitative surveys and 24 qualitative interviews conducted with two groups of women living in rural Nicaragua. One group of women (approximately half) were members of a grassroots feminist organization, and the other group lived in nearby communities where the organization did not offer programs. Analyses of the quantitative data provided support for two models: one outlining a psychological process through which involvement in the organization related to women’s increased involvement in reproductive decision-making with their husbands and higher levels of educational aspiration, and a second that linked involvement in the organization to women’s increased engagement in community support activities. Findings from the qualitative data provide insight into three themes: (1) how specific features of the organization impacted women; (2) how participation in a feminist empowering setting impacted women’s sense of identity, and (3) how involvement in the organization related to women’s goals for their communities and ability to create change consistent with these goals. Overall findings from this research are valuable to both social psychological researchers and groups seeking to enhance social justice and uphold feminist values of equity and community well-being.

Existing High-Level Synthesis (HLS) Systems typically assume a simple representation for the functionality of RT components and for the binding of abstract behavioral (HDL) operators to RT components. Such a representation scheme simplifies synthesis but ignores the problems of representing realistic RT components that may perform several functions and generate several outputs in a single time step. In this paper, we present a novel representation scheme that links realistic RT-component behavior with abstract HDL behavior. It is useful for representing specific components in user-extendable libraries and adapting component libraries to HDL modeling styles. The representation can also be used to support interactive allocation and binding of components during HLS, as well as interactive rebinding of components once a preliminary floorplan is obtained. This allows the designer to iterate between the results of physical design and the higher-level tasks of component allocation and binding. Furthermore, the representation we describe can be used to establish formally the correctness of interactive binding using realistic RT components. We briefly describe the features of the representation and show its applicability on a HLS benchmark - the AM2901.

The evolution of quantum algorithms threatens to break public key cryptography in polynomial time. The development of quantum-resistant algorithms for the post-quantum era has seen a significant growth in a field called post quantum cryptography (PQC). Polynomial multiplication is the core of Ring Learning with Error (RLWE) lattice based cryptography (LBC) which is one of the most promising PQC candidates. In this work, we design Number Theoretic Transform (NTT) based polynomial multipliers and synthesize on a Field Programmable Gate Array (FPGA). NTT is performed using the pipelined R2SDF and R22SDF Fast Fourier Transform (FFT) architectures. In addition, we propose an energy efficient modified architecture (Modr2). The NTT-based designed polynomial multipliers employs the Modr2 architecture that achieve on average 2× better performance over the R2SDF FFT and 2.4× over the R22SDF FFT with similar levels of energy consumption. Polynomial multiplication using the Modr2 architecture developed in this thesis shows 12.5× energy efficiency over the state-of-the-art convolution-based polynomial multiplier and 4× speedup over the systolic array NTT based polynomial multiplier for polynomial degrees of 1024, demonstrating its potential for practical deployment in future designs.

Multiple functional unit architectures have become increasingly widespread since they represent a viable design technique that allows to boost performance by concurrently executing many operations. Technology, though, allows the design of register files providing enough data-!bandwidth to support only few fast pipelined functional units.

One of the possible solutions is to partition the set of registers in multiple banks, each providing only part of the overall bandwidth required, and connect them to functional units by mean of a network.

This design scheme provides a non homogeneous register space requiring code with variables partitioned among the set of register files. Standard register allocation techniques are not suited for this task because of the different kind of resources that must be taken into consideration.

In this report we present a hypergraph-based paradigm that allows to model the process of partitioning; a coloring algorithm is used to assign variables to register files and if a legal coloring is not found, the code is partially rescheduled to allow the algorithm to proceed.

Experiments ran on a set of benchmarks show how the technique can frequently find a legal partitioning of variables without the needs for rescheduling; even when this is not possible, and code must be reorganized, very little performance degradation is usually introduced.

advances in computing steadily erode computer security at its foundation, calling for fundamental innovations to strengthen the weakening cryptographic primitives and security protocols. While many alternatives have been proposed for symmetric key cryptography and related protocols (e.g., lightweight ciphers and authenticated encryption), the alternatives for public-key cryptography are limited to post-quantum cryptography primitives and their protocols. In particular, lattice-based cryptography is a promising candidate, both in terms of foundational properties, as well as its application to traditional security problems such as key exchange, digital signature, and encryption/decryption. At the same time, the emergence of new computing paradigms, such as Cloud Computing and Internet of Everything, demand that innovations in security extend beyond their foundational aspects, to the actual design and deployment of these primitives and protocols while satisfying emerging design constraints such as latency, compactness, energy efficiency, and agility. In this thesis, we propose a methodology to design programmable hardware accelerators for lattice-based algorithms and we use the proposed methodology to implement flexible and energy-efficient post-quantum cache- and DMA-based accelerators for the most promising submissions to the NIST standardization contest. We validate our methodology by integrating our accelerators into an HLS-based SoC infrastructure based on the X86 processor and evaluate overall performance. In addition, we adopt the systolic architecture to accelerate the polynomial multiplication, which is the heart of a subset of LBC algorithms (i.e., ideal LBC), on the field-programmable gate arrays (FPGAs). Finally, we propose a high-throughput Processing In-Memory (PIM) accelerator for the number-theoretic transform (NTT-) based polynomial multiplier.