Scheduling estimation in system level design plays an important role in estimating design metrics of a hardware implementation. Moreover, accurate estimates based on a realistic design model are usually expected. In this report, we present techniques for scheduling estimations based on a control/datapath pipelining architecture. Schedules are computed under both resource and architectural constraints. The resource allocation includes not only functional units but also storage and communication units. Our techniques enable designers to obtain fast and accurate estimates of scheduling.

This paper presents a novel usage-based characterization method to capture predesigned complex functional blocks for automatic reuse in behavioral synthesis. We identify attributes necessary for reuse of such complex components and illustrate how the attributes are captured into a design database. A complex component MT X_MU LT8X8, which computes product of two 8 x 8 matrices, is captured with the proposed method, and its reuse in behavioral synthesis is demonstrated with design of a DCT example. Feasibility of the method for capturing various components is demonstrated as well.