A primary design goal for VLSI systems is to achieve low energy consumption while maintaining high performance. Increasing thermal densities and the portability of emerging computing systems demand further reduction of design power. However, in integrated-circuit (IC) designs, there is a tradeoff between energy and performance, and the solution space for any given design is bounded by the lowest possible energy and the highest possible performance. To minimize energy consumption under performance constraints, we seek to optimize the design up to the Pareto frontier of energy versus performance. Many system- and design-level techniques have been introduced to extend the achievable energy-performance envelope. For low-power IC implementation, this thesis first explores traditional design methodologies, which include gate sizing optimization and power gating. Gate sizing is an effective approach to optimize the tradeoff of power and delay in VLSI design. A sensitivity-guided metaheuristics approach is presented for high-quality, large-scale gate sizing. The proposed gate sizing method can minimize the power (energy) consumption under the timing (performance) constraint. Power gating is one of the most effective solutions available to reduce leakage power. However, power gating has not been practically usable in an active mode. In this thesis, a data-retained power gating is presented to enable power gating of flip-flops during the active mode. Extensions of the energy-performance envelope can be achieved with new system- and design-level techniques such as (i) error-tolerant design, (ii) dynamic voltage and frequency scaling (DVFS), (iii) approximate arithmetic design, and (iv) adaptive power gating. However, with the new system-level techniques for energy-efficient design, conventional CAD flows or designs may constrain or reduce the benefits realized from these techniques; hence, new design methodologies are necessary for each technique. The innovative techniques proposed in this thesis exploit the system and application information, and connect them into design optimization and physical implementation to enable more energy-efficient designs. In other words, if we have better communication between system design and chip implementation, we can improve the design quality in terms of the low energy consumption. First, error-tolerant design allows timing errors, so frequently exercised paths should be optimized to reduce the error rate of the design. This means that a function-aware design optimization is required for the error-tolerant design. Second, to minimize lifetime energy in DVFS design, operating scenarios should be considered and scenario- aware optimization is required. Third, for the approximate designs, a tradeoff between data accuracy and power reduction can be used. Finally, to make an adaptivepower gating, we should retain internal data and control wake-up overheads. In each of these four directions, this thesis proposes novel optimization and design flows which expand the achievable envelope of low-power, high-performance VLSI system design
