Scanning probe lithography is used to directly pattern monolayer transition metal dichalcogenides (TMDs) without the use of a sacrificial resist. Using an atomic-force microscope, a negatively biased tip is brought close to the TMD surface. By inducing a water bridge between the tip and the TMD surface, controllable oxidation is achieved at the sub-100 nm resolution. The oxidized flake is then submerged into water for selective oxide removal which leads to controllable patterning. In addition, by changing the oxidation time, thickness tunable patterning of multilayer TMDs is demonstrated. This resist-less process results in exposed edges, overcoming a barrier in traditional resist-based lithography and dry etch where polymeric byproduct layers are often formed at the edges. By patterning monolayers into geometric patterns of different dimensions and measuring the effective carrier lifetime, the non-radiative recombination velocity due to edge defects is extracted. Using this patterning technique, it is shown that selenide TMDs exhibit lower edge recombination velocity as compared to sulfide TMDs. The utility of scanning probe lithography towards understanding material-dependent edge recombination losses without significantly normalizing edge behaviors due to heavy defect generation, while allowing for eventual exploration of edge passivation schemes is highlighted, which is of profound interest for nanoscale electronics and optoelectronics.

The reduction of carrier recombination processes by surface passivation is vital for highly efficient crystalline silicon (c-Si) solar cells and bulk wafer metrological characterization. Herein, we report a dip coating passivation of silicon surfaces in ambient air and temperature with Nafion, achieving a champion effective carrier lifetime of 12 ms on high resistivity n-type c-Si, which is comparable to state-of-the-art passivation methods. Nafion is a nonreactive polymer with strong Lewis acidity, thus leading to the formation of a large density of fixed charges at silicon surface, 1-2 orders of magnitude higher than what is achievable with conventional thin-film passivation layers. Notably, Nafion passivates the c-Si surface only by the fixed charges without chemical modification of dangling bonds, which is fundamentally different from the common practice of combining chemical with field-effect passivation. This dip coating process is simple and robust, without the need for complex equipment or parameter optimization as there is no chemical reaction involved.

Monolayer 2D transition metal dichalcogenides (TMDCs) have shown great promise for optoelectronic applications due to their direct bandgaps and unique physical properties. In particular, they can possess photoluminescence quantum yields (PL QY) approaching unity at the ultimate thickness limit, making their application in light-emitting devices highly promising. Here, large-area WS2 grown via chemical vapor deposition is synthesized and characterized for visible (red) light-emitting devices. Detail optical characterization of the synthesized films is performed, which show peak PL QY as high as 12%. Electrically pumped emission from the synthetic WS2 is achieved utilizing a transient-mode electroluminescence device structure, which consists of a single metal–semiconductor contact and alternating gate fields to achieve bipolar emission. Utilizing this aforementioned structure, a centimeter-scale (≈0.5 cm2) visible (640 nm) display is demonstrated, fabricated using TMDCs to showcase the potential of this material system for display applications.

Defects in conventional semiconductors substantially lower the photoluminescence (PL) quantum yield (QY), a key metric of optoelectronic performance that directly dictates the maximum device efficiency. Two-dimensional transition-metal dichalcogenides (TMDCs), such as monolayer MoS₂, often exhibit low PL QY for as-processed samples, which has typically been attributed to a large native defect density. We show that the PL QY of as-processed MoS₂ and WS₂ monolayers reaches near-unity when they are made intrinsic through electrostatic doping, without any chemical passivation. Surprisingly, neutral exciton recombination is entirely radiative even in the presence of a high native defect density. This finding enables TMDC monolayers for optoelectronic device applications as the stringent requirement of low defect density is eased.

One of the major challenges in the van der Waals (vdW) integration of two-dimensional (2D) materials is achieving high-yield and high-throughput assembly of predefined sequences of monolayers into heterostructure arrays. Mechanical exfoliation has recently been studied as a promising technique to transfer monolayers from a multilayer source synthesized by other techniques, allowing the deposition of a wide variety of 2D materials without exposing the target substrate to harsh synthesis conditions. Although a variety of processes have been developed to exfoliate the 2D materials mechanically from the source and place them deterministically onto a target substrate, they can typically transfer only either a wafer-scale blanket or one small flake at a time with uncontrolled size and shape. Here, we present a method to assemble arrays of lithographically defined monolayer WS2 and MoS2 features from multilayer sources and directly transfer them in a deterministic manner onto target substrates. This exfoliate-align-release process - without the need of an intermediate carrier substrate - is enabled by combining a patterned, gold-mediated exfoliation technique with a new optically transparent, heat-releasable adhesive. WS2/MoS2 vdW heterostructure arrays produced by this method show the expected interlayer exciton between the monolayers. Light-emitting devices using WS2 monolayers were also demonstrated, proving the functionality of the fabricated materials. Our work demonstrates a significant step toward developing mechanical exfoliation as a scalable dry transfer technique for the manufacturing of functional, atomically thin materials.

The application of strain to semiconductors allows for controlled modification of their band structure. This principle is employed for the manufacturing of devices ranging from high-performance transistors to solid-state lasers. Traditionally, strain is typically achieved via growth on lattice-mismatched substrates. For two-dimensional (2D) semiconductors, this is not feasible as they typically do not interact epitaxially with the substrate. Here, we demonstrate controlled strain engineering of 2D semiconductors during synthesis by utilizing the thermal coefficient of expansion mismatch between the substrate and semiconductor. Using WSe₂ as a model system, we demonstrate stable built-in strains ranging from 1% tensile to 0.2% compressive on substrates with different thermal coefficient of expansion. Consequently, we observe a dramatic modulation of the band structure, manifested by a strain-driven indirect-to-direct bandgap transition and brightening of the dark exciton in bilayer and monolayer WSe₂, respectively. The growth method developed here should enable flexibility in design of more sophisticated devices based on 2D materials.Strain engineering is an essential tool for modifying local electronic properties in silicon-based electronics. Here, Ahn et al. demonstrate control of biaxial strain in two-dimensional materials based on the growth substrate, enabling more complex low-dimensional electronics.

Two-dimensional (2D) noble-metal dichalcogenides exhibit exceptionally strong thickness-dependent bandgaps, which can be leveraged in a wide variety of device applications. A detailed study of their optical (e.g., optical bandgaps) and electrical properties (e.g., mobilities) is important in determining potential future applications of these materials. In this work, we perform detailed optical and electrical characterization of 2D PdSe2 nanoflakes mechanically exfoliated from a single-crystalline source. Layer-dependent bandgap analysis from optical absorption results indicates that this material is an indirect semiconductor with bandgaps of approximately 1.37 and 0.50 eV for the monolayer and bulk, respectively. Spectral photoresponse measurements further confirm these bandgap values. Moreover, temperature-dependent electrical measurements of a 6.8-nm-thick PdSe2 flake-based transistor show effective electron mobilities of 130 and 520 cm2 V-1 s-1 at 300 K and 77 K, respectively. Finally, we demonstrate that PdSe2 can be utilized for short-wave infrared photodetectors. A room-temperature specific detectivity (D) of 1.8 × 1010 cm Hz1/2 W-1 at 1 μm with a band edge at 1.94 μm is achieved on a 6.8-nm-thick PdSe2 flake-based photodetector.

III-V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III-Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)-coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III-Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.

III-V compound semiconductors are widely used for electronic and optoelectronic applications. However, interfacing III-Vs with other materials has been fundamentally limited by the high growth temperatures and lattice-match requirements of traditional deposition processes. Recently, we developed the templated liquid-phase (TLP) crystal growth method for enabling direct growth of shape-controlled single-crystal III-Vs on amorphous substrates. Although in theory, the lowest temperature for TLP growth is that of the melting point of the group III metal (e.g., 156.6 °C for indium), previous experiments required a minimum growth temperature of 500 °C, thus being incompatible with many application-specific substrates. Here, we demonstrate low-temperature TLP (LT-TLP) growth of single-crystalline InP patterns at substrate temperatures down to 220 °C by first activating the precursor, thus enabling the direct growth of InP even on low thermal budget substrates such as plastics and indium-tin-oxide (ITO)-coated glass. Importantly, the material exhibits high electron mobilities and good optoelectronic properties as demonstrated by the fabrication of high-performance transistors and light-emitting devices. Furthermore, this work may enable integration of III-Vs with silicon complementary metal-oxide-semiconductor (CMOS) processing for monolithic 3D integrated circuits and/or back-end electronics.