Power conversion circuits are essential components in every electronic device from laptops and cellphones to wearable and implantable devices. These circuits convert the DC voltage of the battery or energy source to the appropriate DC level or AC form required by a load. The key challenge of this class of circuits is that they often define the size and energy of an electronic system. This is since the volume-size and quality-factor of the required inductors render power conversion circuits disproportionately large and lossy to the rest of the electronic system.

This work aims to make power conversion circuits smaller without losing power efficiency by developing new circuit topologies that primarily rely on capacitors instead of inductors. The developed switched capacitor DC-to-DC and DC-to-AC converters rely on architecting the governing current and voltage equations such that they follow efficient mathematical formulae to enable the minimum loss and/or the smallest volume size as compared to prior topologies. The developed topologies thus enable switched capacitor converters to be as efficient as the industry's flagship inductor-based solutions, however in orders-of-magnitude smaller size. Moving forward, such an approach of relying on electric instead of magnetic energy transfer enables the exploitation of fabrication-technology feature-size scaling to shrink the total electronic system size beyond what is feasible through today's technologies.

Internet of things (IoT) has greatly improved our understanding and control of the world. By deploying sensors to the environment, different types of environmental parameters can be sensed and with proper processing of the data, such as artificial intelligence, we can observe and control at both the top-level and detail. However, various IoT applications also pose lots of challenges for the integrated circuit design, especially for the power efficiency, speed and size. Solving these problems are the keys to turn the ideas into real and practical design and improve the user experience.

In this dissertation, the circuits and systems design of the IoT sensor is presented and discussed. The power management unit (PMU) is an important block in an IoT sensing system, which determines the maximum performance of the circuit. For lots of applications where it is hard to replace the battery and has limited energy source, the efficiency of the PMU also significantly affects the system lifetime. A fast-response-time, high-power-efficiency and dynamic-range change-pump-based LDO is proposed to solve the trade-off between speed, power consumption and stability. The event-driven mechanism and AC-coupled high-Z feedback loop enable fast detection and response speed with low power. The charge-pump with single power transistor architecture helps the LDO achieve a high dynamic range and low ripple over the entire load range. In addition to the power management unit, the clock generation circuit also significantly affects the system performance and power efficiency. Several techniques are proposed to achieve an energy-efficient fast start-up. With the multi-path feedforward negative resistance boosting and dynamic pulse-width injection technique, the start-up time of different frequency XOs can be greatly reduced without a precise injection oscillator. Last, a battery-powered ion-sensing platform is presented and discussed.

The demand for higher performance radio communication increases every day.Since the radio spectrum occupation is very high, modern radio systems require tomaximize the data rate, through put, and minimize the cost of that radio, its noiseand power consumption. Within the given scenario, there are two major factors,the first is spectrum efficiency and the second one is power efficiency. Former isrelated to maximum data rate within the given spectrum limit and the latter isaddresses by the requiredEb/N0(energy per bit over noise poser spectral density)to demodulate the input signal with small error rate.In this thesis, a low power transceiver is presented in which utilizes a high efficiencymodulation, 16-FSK (frequency shift keying) in which to enhance the power effi-ciency while maintain low power operation using innovative circuits.In addition to the design of the transceiver, a BLE/WiFi compliant transmitter isdesigned that is capable of enhancing the user privacy by randomizing the trans-mitted signal features.The 16-FSK receiver is described in Chapter. 1, 16-FSK transmitter is presentedin Chapter. 2, and the BLE/WiFi transmitter is shown in Chapter. 3. Fig. 0.1demonstrates the ICs designed for each project, respectively from top to bottom.

This dissertation presents energy-efficient schemes for short-range wireless communication for wearable devices. Generally, there are two types of wireless scenarios that happen around the human body. The first case is the data transfer between the wearable devices and the local hub devices, e.g., smartphones and smartwatches, allowing to connect to the external network and centrally control multiple wearable devices. Many researchers had proposed various wireless approaches for this scenario; however, there are still limitations in realistic implementations such as restricted form factors and limited energy sources of wearable devices. To address the barriers and challenges of the previously proposed schemes, my doctoral research introduced a new data transmission concept around the human body using magnetic fields, showing the theoretical background and experimental results that validate that the human body acts as a leaky dielectric waveguide. To demonstrate that the proposed concept can be implemented in the practical application, e.g., Hi-Fi audio streaming for portable headphones, this dissertation describes the design procedure and its measurement results of an energy-efficient ultra-low-power transceiver fabricated with CMOS technology.

The other wireless scenario occurs in a single wearable device, especially a body sensor device. For the practical reasons of accurate health monitoring, the body sensor device needs to be implanted or injected inside the human body, and it should operate in a fully-wireless environment for the portability of the wearable devices. This work presents guidelines for the design and optimization of on-chip coils used for wireless millimeter-scale integrated neural implants as an example of this wireless scenario. Since available real estate of a silicon chip is limited, on-chip coil design involves difficult managing multi-dimension trade-offs amongst the number of turns, trace width and spacing, proximity to other active circuits and metalization, quality factor, matching network performance/size, and load impedance conditions, all towards achieving high data/power transfer efficiency.

A scheme for the sampling and quantization of voltages over time in an integrated

circuit chip is presented based on first frequency modulating the signal of interest

and then sampling and quantizing its frequency modulated representation. When

a single input signal is considered and demodulation to recover the original signal is

performed on the same chip as modulation, the resulting structure is an FM-ADC as

discussed in Chapter 2. The recording of multiple input signals using multiple frequency

modulating chips and frequency domain multiplexing combined with demodulation

off-chip is referred to as a distributed multi-channel FM-ADC with demodulation

offloading, and is discussed in Chapter 3 as applied to biopotential signal acquisition as

it offers unique advantages in that application space. Chapter 4 deals with theoretical

optimization of the FM-ADC in both its single-channel and multi-channel forms.

Today, internet of things (IoT) connect the world in way more than we ever thought possible, changing the way we live, work, and interact with each other. Power management has an important role in a successful IoT deployment. Building an efficient, low-cost, and compact power management unit (PMU) becomes a key for enabling remote, long-lived, and small wearable and IoT devices. Thus, this thesis presents miniaturized, efficient, and low cost power management solutions using innovation on both the architecture and circuit level.

The wireless sensor network (WSN) modules of next generation IoT and wearable devices will be implemented on a single system on a chip (SoC) platform that can ultimately combine digital, analog/mixed signal, and RF to provide the highest level of integration and conservation of area. Most of IoT SoC designs will be implemented in FDSOI technology which is available in small geometry processes to merge the benefits of ultra-low power as well as high performance. Accordingly, the proposed power management solutions for IoT and wearable devices in this thesis, fabricated in 28nm FDSOI to be integrated on the same die as the WSN modules.

Energy harvesting is an essential concept for the future of power management in IoT to enable autonomous operation that doesn’t require battery charging or replacement. Thus, the first part of the thesis presents a power management unit that meets the need of small-form-factor net-zero energy systems by aggregating the maximum available power from three different energy sources while simultaneously regulating three output power rails over a wide dynamic load range, while also managing the charging and discharging of a battery, all in a single-stage single-inductor converter. IoT and wearable devices are powered by efficient and durable Li-ion batteries with voltage range 2.8-4.2V. Thus, the second part presents a fully integrated Li-ion compatible hybrid DC-DC converter that meets the needs of small-form-factor IoT while offering superior performance compared to prior-art fully-integrated converters. The challenges of implementing a high-voltage tolerant DC-DC converter with high conversion ratio, using low voltage transistors and poor quality on-chip passives on 28nm FDSOI addressed. The third part presents a miniaturized Li-ion compatible hybrid single-inductor multi-output (H-SIMO) that independently regulates three different output power rails while combining the hybrid topology benefits for compact and efficient implementation. The last part focuses on finding the maximum number of levels and possible multilevel

configurations for a given number of capacitors.

Exploring advancements in implantable neural recording systems stands as the cornerstone of this research endeavor. This thesis presents a comprehensive exploration into the development of advanced implantable neural recording systems. Three novel systems are detailed: a low-power area-efficient Neural Recording System for high-density neural implant applications, a digitally-assisted multi-channel neural recording system, and a multi-channel bidirectional neural recording and stimulation system on chip (SoC).The first system utilizes a Time Division Multiple Access (TDMA) method, achieving simultaneous recordings from 16-neural electrodes. Employing a Least Mean Squares (LMS) algorithm and a single-tap digital adaptive filter (AF), it successfully cancels slowly varying electrode offsets, offering an integrated on-chip solution with high per-channel power and area efficiency. The second system leverages a chopper-stabilized TDMA scheme, significantly reducing integrated noise across various neural signal bands. Furthermore, it introduces an impedance booster module based on a Sign-Sign Least Mean Squares (LMS) adaptive filter (AF), enhancing the AFE input impedance while saving area and power. The third system employs a 16-channel recording TDMA scheme coupled with a novel power and area-efficient stimulation artifact canceller module using an Infinite Impulse Response (IIR) recursive Least Squares (RLS) adaptive filter (AF). Detailed comparisons and analyses of various approaches for artifact suppression are provided. The systems are designed and fabricated in 65nm CMOS technology, offering competitive per-channel area and power consumption while achieving low input-referred noise levels over specific action-potential (AP) and local-field potential (LFP) bands while maintaining high noise efficiency factor (NEF). This thesis not only presents cutting-edge neural recording advancements but also evaluates their performance, paving the way for future developments in neural interfacing technology.

Low-power wireless receiver design has been an active area of research during thelast decade. One of the most difficult part of the design is generating a spectrally pureclock signal for demodulation in an energy efficient manner. The clock generation is usuallydone through either a phase-locked loop, and the energy cost of implementing a PLL isusually more power expensive than the the rest of the receiver. Therefore, the solutionsthus far have been to use a simple modulation schemes such as On-Off-Keying(OOk).However, such modulation schemes are spectrally inefficient, and as the density of wirelessdevices grow larger, more stringent spectral efficiency will be demanded even for low-powerxiv

applications. This dissertation presents a search for an alternative to an envelope-detector.We have investigated a PLL-less coherent detection, as well as an ultra-low power PLLfor an alternative to an envelope detector. Chapter 1 describes the general link budgetrequired for such low-power applications. Popular low-power receiver architectures aredescribed in this chapter. Chapter 2 presents a PLL-less receiver architecture that employs asuper-regenerative oscillator as a phase storage element. The chapter details the system leveland circuit design as well as the measurement results. Chapter 3 presents a mathematicalmodel for super-regenerative reception of phase-modulated signal. The theoretical modelneeded to build the receiver presented in chapter 2 was not available at the time of the design.The authors investigated the behavior of super-regenerative receivers when it is used toreceive phase-modulated signals employing modulations such as phase-shift-keying (PSK).Chapter 4 describes a low-power PLL architecture that is promising enough to meet boththe power and the noise requirement of low-power wireless communication applicationsat 2.4 GHz. The in-band phase noise of sub-sampling PLL can approach the theoreticallimit of the reference phase noise. However, SSPLL can suffer from a significant spurioustone. This chapter presents a sub-sampling PLL architecture that can lower the spurioustone significantly without relying on a power-expensive calibration scheme. Furthermore,the entire loop (except the oscillator) consumes less than 500 microwatts of power, and thetotal power consumption of the PLL is less than 1 mW, suitable for low-power wirelesscommunication applications

As the size of the electronics in mobile and IoT devices scales down while performance demands scale up, power management integrated circuits (PMICs) face increasing pressure to provide highly efficient conversion in increasingly small areas. Most modern mobile devices are powered from Li-ion batteries that operate between 3-5 V. However, the system-on-chips (SoCs) that are powered in such systems are typically operating at < 1.2 V, requiring DC-DC converters that can provide high continuous conversion ratios up to 15x. Ideally, this DC-DC converter should both be efficient in order to maximize battery lifetime, and also small in order to minimize device volume. Unfortunately, for a given topology and packaging technology, there is typically a direct trade-off between efficiency and power density making the achievement of an acceptable trade-off point for a DC-DC converter more challenging.

This thesis introduces new topologies and techniques that help ease this trade-off between efficiency and power density while providing additional benefits like enhanced light load efficiency and reduced input noise and EMI. The first part of the thesis introduces a passive-stacked 3rd order buck (PS3B) converter that offers loss-, structure-, and noise-related benefits as compared to a conventional buck converter. Specifically, all the passives including two inductors are stacked in a packaging-friendly manner at the converter input, allowing for the inductors to process lower current than a conventional buck converter while inherently filtering input current noise. In the second part, a charge recycling technique is applied to the PS3B converter which enables direct reciprocal recycling of gate charge from one power MOSFET to the other, all without affecting converter operation or control. To directly power an SoC from a Li-ion battery while using low-voltage transistors, the third part introduces a symmetric modified multilevel ladder converter that, as compared to conventional flying-capacitor multilevel converters, features reduced conduction losses, naturally balanced flying capacitors, and internal generation of all the supplies required for drivers and level shifters. To combine the benefits of the PS3B converter (inductors processing continuous current on the low-current side of the converter) with the benefits of multilevel converters (Li-ion battery compatibility with low-voltage transistors, and reduced inductor size), an inductor-first flying-capacitor multi-level (FCML) converter is introduced. Prototypes of the presented topologies and techniques achieve state-of-the-art numbers in terms of efficiency, power density, light load efficiency and noise performance.