CPUs and dedicated accelerators (namely GPUs and FPGAs) continue to grow increasingly large and complex to support todays demanding power and performance requirements. Designers are tasked with evaluating the performance and power of increasingly large design spaces during pre-silicon design. Validating and evaluating the performance during the pre-silicon stage catches performance and device issues in advance of fabrication. This reduces time-to-market by reducing the bugs that must be found and fixed after manufacturing, or after synthesizing an FPGA accelerator using high-level synthesis tools.

Cycle-accurate simulators are integral to architectural design and are often the only tool at computer architects’ disposal to evaluate workloads on architectural design points in advance of manufacturing. To enable optimization of the architecture without the exorbitant cost of repeatedly fabricating designs, a high-level of simulator precision is required. As such, the simulators are compute intensive, limiting the number of simulations, and thus workloads or design points that can be evaluated before manufacturing. Historically the computational cost of simulation is absorbed, which slows down time to market and increases the cost of development.

Machine Learning and statistical prediction models have emerged as viable tools to avoid repeated cycle accurate simulations by accurately predicting the metrics generated by cycle-accurate simulators. After one-time model training, the predictive models can then be used in lieu of simulation. Here I will present my research into the development of machine learning frameworks for GPU and FPGA architectures, which leverage cross-architecture predictive statistical modeling to significantly reduce the time required to evaluate workloads and architectural design points.