The reliability of Very Large Scale Integration (VLSI) circuits is crucial in modern electronic devices. VLSI circuits, which contain millions of transistors, are vulnerable to a variety of reliability issues such as electromigration (EM), time-dependent dielectric breakdown (TDDB), and temperature variation. These issues can lead to circuit failure and reduce the lifetime of electronic devices. Traditionally, VLSI reliability analysis and prediction have been performed using physics-based models and simulators. These models, however, are computationally intensive and can be time-consuming to run. In recent years, machine learning (ML) techniques have been used to predict and diagnose reliability issues in VLSI circuits. This thesis presents an in-depth study of machine learning techniques applied to EM analysis, post-silicon thermal map estimation, and electrostatics analysis. Specifically, the first segment proposes two data-driven ML methods for the fast prediction of transient EM stress of general interconnects in VLSI circuits. The traditional numerical partial differential equation (PDE) problem is treated as an image processing or graph aggregation problem which yields considerable speedup with acceptable accuracy. However, these methods are still supervised learning approaches, requiring extensive training data generated from numerical solvers. Therefore, the second segment proposes a hierarchical physics-informed neural networks (PINN) based method for EM analysis. This approach leverages PINN, which is trained mainly by physics laws with minimal labeled data requirements. The hierarchical nature of interconnects is leveraged, and the entire interconnect tree is solved step by step. Temperature variation has always been problematic in VLSI circuits, as reliability degrades drastically as temperature varies. The third segment presents a real-time thermal map estimation method for commercial VLSI circuits. This approach treats thermal modeling as an image-generation task using generative neural networks (GANs), producing tool-accurate thermal map estimations. Electrostatics analysis is an essential step for analyzing TDDB, an important failure mechanism for interconnects. Lastly, the fourth segment presents a PINN-based 2D electric field analysis method. This approach eliminates the heavy dependence of finite element methods (FEM) used in traditional TDDB analysis and leads to orders of magnitude of speedup.

Model order reduction (MOR) is an efficient technique to reduce the complexity of dynamical systems while producing a good approximation of the input and output behavior. Classical MOR approaches such as Krylov subspace and truncated balanced realization methods have been well developed in the areas of system, control, and applied math for general systems in state-space equations. In recent years, MOR techniques using Krylov subspace algorithm have been studied intensively in the field of electronic design automation (EDA) for interconnect analysis.

Interconnects in integrated circuits (IC) can be extracted as RLC circuits, which are described by a class of state-space equations with special structure properties such as symmetry, positive semi-definiteness and sparsity. As a result, to reduce the complexity of interconnect circuits, we can take advantage of the special structures to simplify the classical MOR methods. On the other hand, there are also some special requirements for interconnect reduction: scalability to large problems, passivity and structure preserving, and application to circuits with massive ports. In this thesis, we present several non-Krylov subspace MOR techniques for interconnect analysis.

First, we present new methods based on classical balanced truncation for interconnect analysis: we generalize the simultaneous diagonalization algorithm for first-order balanced truncation to overcome the high computing costs; we also propose a passive second-order balanced truncation technique (and its fast version) to preserve both passivity and structure information inherent to circuit formulation.

Second, we propose two new methods to perform passive reduction: we present new algorithm based on the Caratheodory extension, which has a similar computational cost as the Krylov subspace based methods but ensures the passivity of reduced model without any restriction on the internal structure of state-space equation; we also propose the concept of conditional passivity and a method to generate frequency band-limited passive reduced models.

Finally, we work on long-standing problem of reducing interconnect circuits with massive ports. We propose a decentralized MOR scheme, where a multi-input multi-output (MIMO) system is decoupled into a number of subsystems in terms of outputs. The decoupling process and terminal reduction are based on the relative gain array (RGA), which measures the degree of interaction of each input-output pair. The reduction scheme can lead to passive reduction and is suitable for resistive coupling dominatant networks like power grids and substrate networks.

Power, thermal, and related reliability issues are among the major limiting factors for today’s high performance multi-core processors. This is especially true after the breakdown of the so-called Dennard scaling, since power density starts to increase as IC technology advances. To enhance reliability, researchers have proposed many power/thermal regulation or dynamic management methods, including clock gating, power gating, dynamic voltage and frequency scaling (DVFS), and task migration. In this thesis, we present our findings to address the challenges of post-silicon power and thermal characterization, and dynamic thermal managements for lifetime reliabilities. We first address the problem of accurate full-chip power and thermal map estimation for commercial off-the-shelf multi-core processors. The novel scheme is developed to generate the true 2D power density maps based on the thermal measurements of the processor with backside cooling and facilitated with an advanced infrared (IR) thermal imaging system. the proposed method achieves both higher resolution and considerable speedup than a recently proposed state-of-art method. Then the second, we propose a novel approach for the real-time estimation of chip-level spatial power maps for commercial TPU chips based on a machine-learning technique for the first time. In detail, we achieve estimating the spatial power for commercial TPUs from the hyperparameters of the neural networks (workloads) that are deployed on the TPUs in real-time. Thirdly, processors operating with heat sink cooling remains a challenging problem due to the difficulty in direct measurement. We build an FEM model to reconstruct the full-chip thermal maps for commercial processors while they are under heat sinks. Lastly, based on the spatial power characterization, we propose a new dynamic thermal and reliability management framework via task mapping and migration to improve the thermal performance and lifetime reliability of commercial multi-core processors. Compared to the existing works, the new approach is the first to optimize VLSI reliabilities by exploring workload-dependent power hot spots. The advantages of the proposed method over the Linux baseline task mapping and the temperature-based mapping method are demonstrated and validated on real commercial processors.

Approximate computing enables efficient trade-off among accuracy,area, latency and power for more efficient error tolerant applications implementation such as machine learning and multimedia workloads. Those workloads are heavily dominated by the arithmetic operations and hence designs of hardware-efficient approximate arithmetic units have been intensively investigated recently. However, most of the existing works lack the systematic configurability for accuracy vs. area/power/latency trade-off. This thesis merges several works into designs of fast approximate arithmetic units with improved accuracy and hardware efficiency. The first work proposes a new counter-based stochastic-behaving approximate integer unsigned multiplier and scaling method with improved counting efficiency for many emerging error tolerant application workloads such as deep neural networks, mitigating a long-standing issue of the stochastic computing that small inputs usually lead to large error. The second work proposes a novel counting-based SC divider with accelerated counting process and improved accuracy to easily interface with the existing stochastic or binary logic. The third work focuses on improving the accuracy and the hardware efficiency of the conventional approximate logarithmic multiplier at the same time with a novel error compensation scheme. Last but not least, the forth work mitigates an important problem that approximated designs might lead to unwanted higher temperature and related reliability issues due to the increased power density and proposes a power density aware approximate logarithmic multiplier design which can reduce the power density of the original approximate logarithmic multiplier design with no accuracy loss.

As integration scales to the 20nm regime and below, the integrated circuit (IC) design has seen the billion transistor counts. For instance, the latest Pascal GPU using 16nm FinFET technology from Nvidia has 150 billion transistors. As a result, it becomes very challenging to verify those billion-transistor chips and there is an urgent need to develop advanced and parallel simulation technique. On the other hand, the counterfeit ICs have become a major security threat for commercial and mission-critical systems. In addition to the huge economic impacts, they post significant security and safety threats on those systems. The objective of this thesis is to develop new techniques to address above two tough issues encountered in VLSI research: new fast parallel circuit simulation and potential solutions to mitigate the counterfeit IC problem.

To accelerate the circuit simulation, we study several important linear algebra operations in simulation steps, such as sparse matrix-vector multiplication (SpMV), direct linear LU factorization and iterative general minimum residual linear solver. Parallel computing such as general purpose GPU programs are good solutions for improving performance of these operations. We apply GPU for these tasks and attain impressive speedup over traditional or CPU methods. All algorithms and implementations are demonstrated with representative numerical experiments and thorough comparisons among different methods and platforms.

For various types of counterfeit ICs - recycled, remarked, cloned, out-of-spec, and over-produced, we propose a multi-functional on-chip sensor and post-authentication policy for detecting and preventing them. Especially for recycled ICs, we propose two kinds of aging sensors, which are based on electromigration (EM)-induced aging effects and ring oscillator (RO)-based frequency aging effects. These two aging sensors can effectively detect chip usage time for both short and long periods. Simulated results show the advantage of the proposed multi-purpose sensor against the existing on-chip sensors in terms of functionality, detection coverage and usage time estimation range and accuracy.

Failures introduced by the electromigration (EM) effect in copper interconnect is one of the top reliability issues in modern integrated circuits (ICs) in 10 nm technology and below. International Technology Roadmap for Semiconductors (ITRS) predicts that the required current density for driving a normal gate will exceed the EM current density limit in 2024 if the industry continues current technology scaling with existing interconnect materials and EM design rules based on current density.

Because of EM effect, under extreme current densities, copper interconnect is highly probable to fail over time, most of which is caused by void formation. The behavior of void in copper interconnect, which includes void generation, growth, migration, merging, and vanishing, interacting very tightly with mechanical hydrostatic stress, is critical to the EM reliability. Among the variety void behaviors, void growth and migration dominates the impact on the consequence of open-circuit failures. The analysis of void growth and migration and circuit failures thereby is considerably difficult because of the coupling of a variety physical systems (temperature, electrical current density, void shape, and hydrostatic stress).

In this work, a multi-physics finite element method (FEM) based analysis method for void growth simulation of confined copper interconnects is proposed. The purpose is to facilitate the analysis of void behavior and EM-induced copper interconnect failures. The proposed method for the first time considers four important physics simultaneously in the EM failure process and their time-varying interactions: the hydrostatic stress in the confined interconnect wire, the current density, copper-void boundary evolution, and Joule heating induced temperature. A solver based on finite element method is proposed to solve the coupled systems in time-dependent manner. The proposed work ranges from deriving the partial differential equations governing the interaction of the hydrostatic stress and copper-void boundary evolution, to their variational form derivation, and finally to a software implementation.

The experiment data acquired from the software matches well with the behavior observed in real silicon experiments, which are in the aspects of hydrostatic stress and void shape evolution, final hydrostatic stress distribution, and Joule heating effect.

With increasing power density of latest generation of AI-enabled server racks (e.g. 30-80 kW) along with growing adoption of such servers for deep learning tasks such as image understanding, speech recognition, etc., the energy and cooling requirements of AI-enabled data centers are growing at an alarming rate. In recent years, data center architects have emphasized the importance of holistic approaches to design and operation of data centers by considering both IT equipment and cooling infrastructures; however, a comprehensive design approach for an energy-efficient data center is very limited. This paper details the development of a tool that focuses on energy-efficient design of a data center based on workload predictions, IT configurations, and climatic conditions. Actual measured data are typically not available in the design stage and evaluation of data center energy efficiency, in terms of power usage effectiveness (PUE), solely rely on analytical models. Therefore, in this paper, a thermodynamic-based physical model of an AI-enabled data center configuration, including the cooling system, is developed and benchmarked based on an actual data center. This data center is located at a colocation facility and mainly consist of GPU server nodes with primary application of AI/deep learning research. The colocation center is equipped with a chiller system to create a building chilled water loop, which is used to cool the air flow of air conditioning units (CRAHs) in each data center room. The chilled air from the CRAH units are supplied to an under-floor plenum and eventually enter the data center room through perforated tiles to provide sufficient cooling to the server racks in the cold aisle containment. For benchmarking the data center, power, coolant flow rate, and temperature data are obtained either through the equipment’s monitoring system or via sensor measurements. Comprehensive PUE analysis can be established to determine the most energy-efficient cooling system design and to find the optimal flow rate and temperature set points while meeting design constraints such as geographical location and weather conditions

As technology scales into smaller feature sizes, electromigration (EM) has become a progressively severe reliability challenge due to increased interconnect current densities. It may lead to an increase in wire resistance thus resulting in functional failure of the system. In other words, the reliability of very large scale integrated (VLSI) circuits is increasingly endangered by EM. Therefore, to ensure reliable circuits, it is important to shift today’s design flow from the traditional EM verification towards an EM-aware design methodology.Since power grid wires experience the largest current flows on a chip, they are more susceptible to long-term reliability issues and functional failures. The interconnect wire in power grid networks usually contains multiple segments, which is a multi-segment wire. Generally, the wider the interconnect, the lower the current density and the greater the resistance to EM. On the other hand, during the power grid synthesis in a typical design flow, one important step is to size the wire width of the power grid stripes after the topology of the power supply network has been determined. The area of the power grids is expected to be optimized while EM and excessive IR drop constraints are met. In this dissertation, several EM-aware power grid wire sizing methods are presented to enhance EM reliability in the traditional optimization approaches and speed up the optimization process. Specifically, first, new power grid network sizing techniques based on the novel EM immortality check methods for general multi-segment interconnects have been proposed. Second, by taking EM aging effects into consideration, we have developed two EM lifetime constrained power grid optimization methods to address the overconservative EM immortality constraint. Furthermore, we have proposed a new data-driven fast EM-induced IR drop estimation framework to accelerate full-chip EM-induced IR drop analysis. Last but not least, we have presented novel approaches for localized and global optimization by utilizing the inherent differentiable power of deep neural networks.

The reliability of Very Large Scale Integration (VLSI) circuits is crucial in modern electronic devices. VLSI circuits, which contain millions of transistors, are vulnerable to a variety of reliability issues such as electromigration (EM), time-dependent dielectric breakdown (TDDB), negative bias temperature instability (NBTI) and hot carrier injection (HCI). These issues can lead to circuit failure and reduce the lifetime of electronic devices.This dissertation merged several works to present a study to mitigate the aging effects for VLSI circuits from multiple aspects. Firstly, due to the unidirectional current of the on-chip power grid, its aging effect is dominated by EM, this paper proposed a on-chip power grid EM-aware IR drop prediction method accelerated by machine learning (ML) techniques, and a matching fast EM-aware IR drop fixing method for on-chip power grid. Traditionally, VLSI reliability analysis and prediction have been performed using physics-based models and simulators. These models, however, are computationally intensive and can be time-consuming to run. This thesis paper presented a framework that machine learning techniques is adopted to model full-chip EM-aware IR drop, and a derived fast power grid sizing strategy, which leads to significant speedup over the existing analytical method. Secondly, with the continuous scaling of transistor sizes, the two dominant aging effects on arithmetic circuit and transistors are NBTI and HCI. The NBTI and HCI effects have various impacts such threshold voltage drift for the MOS transistors, device lifetime reduction, and circuit speed slowing down. Hence, this paper adopts stochastic computing techniques to enable an efficient trade-off among accuracy, latency, power, and area for error-tolerant applications.