Electromigration-Aware On-Chip Power Grid Design and Optimization
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Electromigration-Aware On-Chip Power Grid Design and Optimization

Abstract

As technology scales into smaller feature sizes, electromigration (EM) has become a progressively severe reliability challenge due to increased interconnect current densities. It may lead to an increase in wire resistance thus resulting in functional failure of the system. In other words, the reliability of very large scale integrated (VLSI) circuits is increasingly endangered by EM. Therefore, to ensure reliable circuits, it is important to shift today’s design flow from the traditional EM verification towards an EM-aware design methodology.Since power grid wires experience the largest current flows on a chip, they are more susceptible to long-term reliability issues and functional failures. The interconnect wire in power grid networks usually contains multiple segments, which is a multi-segment wire. Generally, the wider the interconnect, the lower the current density and the greater the resistance to EM. On the other hand, during the power grid synthesis in a typical design flow, one important step is to size the wire width of the power grid stripes after the topology of the power supply network has been determined. The area of the power grids is expected to be optimized while EM and excessive IR drop constraints are met. In this dissertation, several EM-aware power grid wire sizing methods are presented to enhance EM reliability in the traditional optimization approaches and speed up the optimization process. Specifically, first, new power grid network sizing techniques based on the novel EM immortality check methods for general multi-segment interconnects have been proposed. Second, by taking EM aging effects into consideration, we have developed two EM lifetime constrained power grid optimization methods to address the overconservative EM immortality constraint. Furthermore, we have proposed a new data-driven fast EM-induced IR drop estimation framework to accelerate full-chip EM-induced IR drop analysis. Last but not least, we have presented novel approaches for localized and global optimization by utilizing the inherent differentiable power of deep neural networks.

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