UC Irvine

Embedded systems are increasingly seeing the need for self-awareness to operate autonomously in the face of uncertainty and unpredictability in the environment, the applications they execute, and in the manufactured hardware. The notion of self-awareness enables a system to monitor its own state and behavior such that it is capable of making judicious decisions and adapt intelligently. However, emerging Multiprocessor Systems-on-chip (MPSoCs), used by these embedded systems and devices, still treat the elements of intelligence, specifically self-awareness, as a second-class design requirement, supporting them with ad hoc and poorly-developed awareness mechanisms, architectural supports, and system software. This dissertation overcomes these limitations by providing the foundation for a new class of self-aware adaptive MPSoCs called a Cyber-Physical-System-on-Chip (CPSoC). Unlike traditional MPSoCs, CPSoCs are distinguished by an intelligent co-design of the control, communication, and computing (C3) infrastructure while considering both the cyber and physical aspects together so as to adaptively achieve desired objectives and goals. CPSoC's sensor-actuator rich scalable architecture intrinsically couples on-chip and cross-layer sensing and actuation to enable self-awareness in a principled way. The thesis corroborates, through experiments and FPGA prototypes, the key idea that giving the SoC the freedom to opportunistically adapt the software and the hardware stack by infusing self-awareness mechanisms and steerable knobs across the stack can open up new and otherwise untapped opportunities in energy efficiency, performance, and thermal resilience.