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Automated Power-Aware System-Level Design with the MAVO Framework

  • Author(s): Samei Syahkal, Yasaman
  • Advisor(s): Doemer, Rainer
  • et al.
Abstract

For the past few decades, semiconductor capabilities have been improving as Moore's law predicted. Transistor size has been shrinking and technology size will be less than 20nm in the near future. These improvements enable designers to come up with more complex systems. However, this has made power dissipation a major design obstacle. Conventionally, power consumption is considered in the later stages of the design process, like the architecture level, Register Transfer Level (RTL), gate level, and physical level, where detailed information about the design is available. Although there are many power-aware design tools at these

lower levels, the simulation and evaluation time are high and often beyond the time-to-market requirements. To tackle the long simulation time as well as avoiding time consuming design modifications at lower levels, designers are raising the level of abstraction to the system level.

Over the last decade, research in Electronic System Level (ESL) design has resulted in significant advances in addressing the rising design complexity and meeting the required performance constraints. Now a major concern of system-level design is power dissipation in System-on-Chip (SoC) which not only affects battery lifetime but also thermal aspects and reliability of the end product. Although power aware design is crucial in ESL design, System Level Description Languages (SLDL) are not supporting this feature natively.

Towards power-aware ESL design, in this dissertation we present MAVO, an automated framework to Monitor, Analyze, Visualize and Optimize both power and performance at the early stages of the design process. The proposed framework supports waveform-based power estimation and optimization for rapid system-level design. MAVO is adapted for automated SoC design and it is integrated to System-on-Chip Environment, a prototype ESL design tool for rapid power-aware design.

We perform different experiments to evaluate the accuracy and fidelity of the framework, including JPEG image encoder, MP3 audio decoder and H.264 video decoder and encoder. Experimental results show that our developed framework can achieve a high degree of fidelity while providing significant speedup.

We also examined MAVO for applying different power optimization mechanisms on a Canny edge detector application. Our studies show large potential for design modification toward power efficient design models at system-level. Additionally we applied MAVO along with

static analyzer tool in order to capture power and performance trade-offs and apply power optimization techniques automatically.

Overall, our work provides an advanced power estimation infrastructure for power- and performance-aware system model development. It can significantly help embedded system designers to build low-power and reliable products in shorter time frame.

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