UCLA

Spintronics is an emerging field that studies the properties of electron spin and discovers the methods to detect and manipulate its associated magnetic moment in a solid-state device, in addition to its fundamental electronic charge. Utilization of spintronic devices has been considered as a possible alternative for beyond CMOS technology. One of the most promising spintronic devices is a magnetic tunnel junction (MTJ) that has attracted the attention of academia and industry owing to its remarkable characteristics such as non-volatility, virtually unlimited endurance, and CMOS compatibility. Also, due to the discovery of the spin-transfer torque (STT) and spin Hall effect (SHE) as new switching mechanisms, a nanosecond switching speed has been demonstrated in MTJ devices. However, these current-driven switching methods inherently cause a significant ohmic loss since they require relatively a large amount current to generate sufficient spin torque. Recently, a voltage-controlled effect has been utilized to mitigate the energy issue by drastically reducing ohmic dissipation during switching in a noble memory architecture called magnetoelectric RAM (MeRAM). In addition to achieving high-energy efficiency, voltage-induced switching leads to further improvement in terms of density and switching speed, opening the door to new possibilities of next generation low-power and high-speed system architectures.

In this dissertation, we explore the characteristics of voltage-controlled magnetic anisotropy (VCMA) effect driven precessional switching based on an MTJ macrospin compact model including the VCMA effect in its built-in Landau-Lifshitz-Gilbert (LLG) equation. In particular, this compact model allows predicting required bias conditions for switching, monitoring the three-dimensional magnetization dynamics, and extracting the write error rate (WER). Furthermore, we demonstrate a wide variety of spintronics-CMOS circuits utilizing unique features of voltage-controlled MTJ for many applications. Overall, the performances of the proposed circuits are improved by an order of magnitude, especially, in terms of energy and area. Also, we develop several practical design techniques to improve the reliability of the read and write operations in MeRAM. Lastly, a synchronous 4Kbit MeRAM macro is designed based on IBM 130 nm technology. After discussing the MeRAM macro specification and constraints, each circuit component of the macro and its verification results are presented.