UC San Diego

The pursuit of secure computation has always featured a tension between performance and security. Security mitigations often come with a high performance cost that can be manifested in serious environmental and economic impacts if they are employed, and in disastrous security and privacy breaches, if not. In the context of processor architectures, the security-performance tension is only growing as new attacks appear, each exploiting a crucial performance optimization, threatening to unwind decades of architectural gains. These hosts of attacks on microarchitectural optimizations painfully coincide with an era in which those performance optimizations are needed most – an era when Moore’s law is fading and Denard’s scaling is gone.

In this dissertation we strive to defuse this security-performance tension by deepening our understanding of vulnerabilities in modern processors, providing efficient hardware support to enable security, and designing new high-performance secure architectures. We first show how performance optimizations can have devastating security implications by introducing a novel microarchitectural side-channel attack that targets Data Direct IO, a network packet processing optimization implemented by Intel (Chapter 1). Then, we propose Context-Sensitive Decoding (CSD), a framework that takes advantage of the instruction-to-micro-op translation that exists in most modern processors to provide security features (Chapter 2). Finally, we propose novel secure and fast architectures to mitigate vulnerabilities in two of the most crucial performance optimizations in modern processors: Speculative Execution (Chapter 3)and Simultaneous Multithreading (Chapter 4).