UC Irvine

Embedded system designers continuously face a twofold challenge handling the ever-

increasing complexity of design and meeting the ever-shrinking time-to-market timeline. To meet such a challenge, the system design paradigm has shifted to platform-based design characterized by intensive use of software and aggressive reuse of verified components. More and more designs are turning to heterogeneous platforms to meet design constraints in multiple criteria. However, the use of such and heterogeneity generates more challenges for platform-based design. To address the challenges, system designers must utilize system-level methodologies for specification and design. Here the designers begin the design process by coming up with a computation model

that captures the behavior of the system. The computation model is successively refined down to the structural model in the system level. In each refinement, the designers explore the design space. The design space comprises a set of alternatives concerning hardware/software partitioning, platform selection, and mapping. The design space is huge, however, necessitating the automation of its exploration. The platform is very often fixed regarding either availability or legacy reasons, making mapping crucial. This dissertation focuses on the automatic mapping of the computation model for the given heterogeneous platform.

This dissertation presents a new automatic mapping technique. The proposed technique consists of two separate phases: initial mapping and improvement driven by cycle-approximate estimation. Existing mapping techniques depend on early estimation so a dilemma arises from the fact that cycle-approximate estimation cannot precede mapping. The dilemma can be gotten around by our performing initial mapping based on rough estimation and then making iterative improvements based on cycle-approximate estimation. While earlier work has been domain specific, the mapping techniques in the proposed work are driven by a general computation model that includes hierarchy, state transitions, dynamic data-oriented behavior, and imperative languages. The proposed work also addresses mapping with an awareness of general hierarchy in pipelined applications. In such a mapping technique, the size of the design space explored is limited by

the speed of cycle-approximate estimation. Earlier work has realized such a fast cycle-approximate estimation by generating and simulating Transaction Level Models. However, simulation has to be performed whenever there is any change in the platform or mapping. That is not necessary and therefore there is still room for improvement regarding speed. This dissertation presents a new trace-driven estimation that is orders of magnitude faster than simulation-based cycle-approximate estimation while losing neither accuracy nor generality.

We have applied the proposed mapping techniques to multiple multimedia applications and the techniques outperformed in terms of execution time the competitors by proportions ranging from 23.3% through 36.3%.