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Uncertainty Propagation in Transistor-level Statistical Circuit Analysis

  • Author(s): Tang, Qian Ying
  • Advisor(s): Spanos, Costas
  • et al.
Abstract

In today's semiconductor technology, the size of a transistor is made smaller and smaller. One of the key challenges presently faced by the designers is the increasing impact of process variations to circuit performances. As a result, circuits designed using the traditional methods can deviate from the desired specifications after being manufactured. Therefore, new circuit design and characterization methodologies are required to handle these process variations.

The problem of estimating the circuit performance at a transistor-level due to parameter uncertainties is examined. Uncertainty in circuit process and device parameters arises as a result of manufacturing variability. Since electrical circuits are, in general, complex and nonlinear systems, estimating their performances efficiently and accurately is very challenging. Existing methods on propagating uncertainties in circuit parameters to circuit performance include worst case corner analysis, Monte-Carlo simulations, response surface modeling, sensitivity analysis and unscented transformation.

In this work, a novel interval based circuit simulation algorithm is proposed. An interval is a quantity consists of noise variables following Gaussian. The algorithm is developed for both Gaussian and non-Gaussian process variations.

When the uncertainty in the circuit process and device parameters can be captured by correlated Gaussian distributions, the process/device parameters are first represented by the appropriate interval representations. An interval-valued SPICE simulator, in which all real number operations are replaced by interval operations, is used to simulate the circuit. The simulation results are therefore interval-values that can be used to extract performance statistics. In this approach, only one circuit simulation is required to obtain the best Gaussian distribution approximation for any circuit performance.

The algorithm is tested on RC circuits and transistor circuits with excellent simulation accuracy (<2% error) as compared to Monte Carlo simulation results. It is shown analytically that the runtime of the interval valued circuit simulation is on the order of O(n+m)O(c3) where n is the average number of noise variables per interval operation, m is the average number of noise variables shared between any two interval quantities and c is the number of nodes in the circuit.

In the case when the process/device parameters cannot be modeled with Gaussian distributions, A Mixture of Gaussian (MOG) distribution is used to approximate all non-Gaussian distributions and a novel extension to the interval representation is proposed. The algorithm is tested on circuit paths of 100 stages containing inverters, NAND gates and NOR gates. The simulation result of the proposed algorithm agrees very well with Monte-Carlo simulation. In addition, the runtime of the proposed algorithm shows a 54X speed up compared to Monte-Carlo simulation.

The proposed interval-value based simulation engine for both Gaussian and non-Gaussian process variations can be directly applied to fast and accurate standard cell library characterization, where the distribution of the cell delay and power are calculated. In addition, the distribution information provided by the proposed simulation method can be feed into statistical timing analysis engine for full-chip level timing closure. The proposed simulation engine can also be incorporated into statistical circuit optimizations.

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