UC San Diego

With the advances in non-volatile memory technologies, the access latencies and bandwidth of storage class memories such as PCM, spin-transfer torque RAMs, have improved three orders of magnitude compared to hard disks. Along with these improvements, internal bandwidth of the solid state drives (SSDs) has increased and has exceeded the bandwidth on the Host Interface. Thus the Host Interface is the performance bottleneck when the SSDs are treated as simple block IO devices. With the decrease in access latency of the new memory technologies, the memory latency is a small fraction of the total access latency from the host. These observations indicate that treating SSDs made of fast memories as just block IO devices will restrict the system performance gains. In this work, we propose an Software-Defined SSD (SDSSD) Architecture that expands the scope of an SSD to a smart device with compute logic. By moving computations inside the SSD, the amount of data transferred to the host is reduced, thereby reducing the impact of the host interface bottleneck. The compute logic is made software programmable enabling different host applications to make use of it. The compute logic and the host applications interact using a generic RPC Interface, thus making programming simple. The proposed architecture is designed and implemented on a FPGA prototyping board. The results from the IO benchmarks run on the SDSSD prototype indicate that, bandwidth and latency of SDSSD Architecture matches closely to the performance of the SSD Architecture with IO specific logic for large access sizes