Unit Time Modelling of Asynchronous and Pulse-Gate Circuits
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Unit Time Modelling of Asynchronous and Pulse-Gate Circuits

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Pulse gates have shown promise as a structured manual methodology for the design of high performance systems. In this paper we present a “unit time” model, identifying the behavior the circuit from its topology. This model is applicable to asynchronous circuits in general but particularly suitable to pulse gate circuits where it agrees well circuit designer assumptions about high performance circuits. We show that for small-to-medium circuits that have a topological “coherence” property, timing constraints can be produced from the unit time model to ensure behavioral correctness of the circuit. To allow complete systems to be verified, we divide the circuit into regions each of which can be modeled by unit time model. We introduce a notion of communication by ”phrases” of events between region that allow coherent communication between separate regions. In this paper, we present a proof that the timing constraints provided by the unit time model are sufficient to ensure behavioral correctness of the circuit in a general bi-bounded sense. Lastly, we also describe an automated software tool that applies this model to pulse gate circuits.

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