A Chip-Level CDM ESD Protection Circuit Modeling and Simulation Method and Experimental Verification
- Author(s): Wang, Han;
- Advisor(s): Wang, Albert;
- et al.
Electrostatic discharge (ESD) failure is one of the most challenging reliability problems to integrated circuits (ICs) and other electronic systems. Industrial statistics suggests that more than 30% of IC failures are caused by ESD or electro overstress (EOS) events, resulting in billions of dollars in losses annually to the industry. Therefore, ESD protection is required for all ICs and other electronic products. There are many different ESD characterization models and standards, such as, human body model (HBM) and charged device model (CDM), which are adapted by the industry. Among these ESD models, CDM ESD failure and protection design is extremely challenging due to the ultrafast nature of CDM ESD pulses.
As the semiconductor process technologies advance to sub-32nm nodes, CMOS gate oxide becomes thinner and the junction becomes shallower, making ICs more susceptible to ESD failure, especially the ultrafast CDM ESD surges. On the other hand, costs for IC designs and fabrication at advanced IC technology nodes has become extremely high, which demands for first-Silicon design success of advanced IC chips. Therefore, full-chip level ESD protection circuit simulation becomes desirable for on-chip ESD protection design, which has been a major challenge in IC designs due to the complexity of ESD protection at full chip level.
Substantial efforts have been devoted to developing full-chip circuit-level ESD protection design simulation techniques in recent years. For example, a chip-level ESD protection circuit simulation method for HBM ESD protection using SPICE was reported in, which allows accurate circuit-level ESD protection simulation. However, for the emerging CDM ESD protection designs, little success has been reported. This is largely due to the fact that CDM ESD events are extremely fast, down to 100ps for the rise time of an CDM ESD pulse, and the distribution of electrostatic charges inside an IC chip in CDM ESD mode is very difficult to model. The state-of-the-art in CDM ESD protection simulation utilizes an over-simplified lumped electrostatic charge distribution model, which does not reflect the real-world problem.
This thesis describes a novel distributed electrostatic charge distribution model and a new circuit-level simulation method to enable accurate full-chip CDM ESD protection circuit simulation, aiming to achieve CDM ESD protection design prediction and hence, first-Silicon design success in developing CDM ESD protection solutions for advanced ICs. The new CDM ESD model and simulation techniques developed was verified in ICs implemented in a commercial 28nm CMOS technology.