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Multi-Gigahertz Synchronous Sampling and Triggering (SST) Circuit with Picosecond Timing Resolution


The Antarctic Ross Ice shelf ANtenna Neutrino Array (ARIANNA) particle physics experiment aims to detect ultra-high energy neutrinos originating outside our solar system. A second generation detector prototype for the experiment has been developed and successfully deployed in Antarctica. The second generation detector is based on the Synchronous Sampling and Triggering (SST) integrated circuit. This dissertation focuses on the design and performance of the SST chip.

Fabricated in a 0.25um CMOS process, the SST is a low power data acquisition circuit that monitors for potential neutrino signals and preserves candidate signals. The waveform capture is performed with a 256-cell time-interleaved sampling array. Continuous sampling operation is achieved through circular cycling across the array. The synchronous sampling clock generation allows for sampling rates that span six orders of magnitude (i.e. ranging between 2.0 KHz and 2.0 GHz). The analog bandwidth (-3dB frequency) of the SST reaches 1.5 GHz, allowing for the capture of frequency components up to the Nyquist frequency. The SST integrates four channels of waveform capture functionality into a single chip.

Each SST channel includes event triggering to initiate the signal capture of neutrino events, and to reject random noise signals. Events are triggered based on outputs from a pair of high speed comparators that monitor for bipolar threshold crossings. Multiple triggering options are available on the SST, including direct output of the comparator signals and triggering on dual threshold crossings occurring within a programmable time window.

The SST chip utilizes an external low jitter LVDS oscillator to synchronously generate an internal sampling clock with low timing jitter. The fixed pattern timing noise was characterized through two different approaches: a stochastic zero crossing method and a Monte Carlo based simulated annealing method. After calibrating for fixed pattern timing noise, the SST achieves inter channel timing resolutions between 1.15 ps (RMS) and 2.36 ps (RMS).

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