Analysis and Design of Precision Timing Circuits using Pulse Mode Event Signaling
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Analysis and Design of Precision Timing Circuits using Pulse Mode Event Signaling

  • Author(s): Mukim, Prashansa
  • Advisor(s): Brewer, Forrest
  • et al.
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This thesis presents an analytical framework and circuit solutions to a host of timing problems that are applicable to systems of varying scales. These non-standard solutions provide higher performance alternatives to the issues of multi-phase clock distribution and larger-scale on-chip or on-interposer communication and coherence. The underlying circuits for all these solutions are pulse mode asynchronous and built using a logic family of gates that encode both data and the time of arrival as atomic pulses. These gates incorporate local negative feedback loops leading to useful dynamic behavior that is exploited in the design of low-noise closed loop timing circuits.First, Collective Pulse Oscillators (or CPOs), the simplest closed loop pulse gate circuits are presented. CPOs achieve FoMs better than conventional ring oscillators, while also providing precise clock phases much finer than the delay of a typical gate in a given technology. The noise analysis of CPOs is based on a time-domain analytical model, which is expanded into a rapid behavioral simulator, and validated against measurement results for different diameter CPOs implemented in 130 nm technology. Next, complex CPO topologies that improve the high-frequency stability of loop-connected CPOs are presented and the potential of such structures in implementing timing distribution networks that utilize distributed feedback to enhance the accuracy of the timing source itself is evaluated. Architecture, design and measurement results for a 5.5 GHz low- jitter transmission-line stabilized pulsed wave oscillator implemented in 130 nm are also presented. Second, Multi-Wire Phase Encoding (MWPE), a transition signaling strategy suitable for on-chip/on-interposer links connecting globally asynchronous modules is presented. These links are aimed at reducing the energy cost of moving data across a large scale SoC or NoC, which is known to be orders of magnitude higher than the cost of computation. MWPE, by encoding data in the time correlated switching of multiple signaling wires allows very high-bandwidth data transmission on band-limited and lossy on-chip wires, with PLL/DLL free data recovery. Theoretical and practical bandwidth limits for MWPE are derived and link performance in 22 nm FDX technology is evaluated. Finally, methods of implementing low cost time-domain linear filters that utilize precise clock phases to reduce timing noise originating from systematic noise sources are presented.

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This item is under embargo until April 30, 2023.