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Statistical Metrics of Hardware Security


Hardware security is a fundamental and increasingly important contributor to the trustworthiness of our computing infrastructure. With the proliferation of embedded computers, attacks focused on exploiting hardware vulnerabilities are being discovered rapidly, and mitigation techniques are being proposed and deployed. But how do we determine the effectiveness of a mitigation against attacks that may not yet exist? Methods that answer this question are called security metrics. In situations where an attack relies on either disruption or interception of non-deterministic values, these security metrics are based on statistics. Statistical metrics are based on assumptions about the capabilities of potential attackers and the nature of the measurements. Metrics with assumptions that are too strong can be a source of false confidence, because a favorable metric result does not necessarily indicate a secure device. In this dissertation, I formulate practical metrics in the context of power side-channel analysis and continuous testing of random number generators that do away with many of these limiting assumptions. This dissertation has three major facets. In the first, I present a hardware system and statistic for continuous testing of random number pipelines which can be used irrespective of the underlying probability distribution and requires minimal a priori knowledge about the system to be monitored. The second, the Holistic Assessment Criterion, is a statistic that allows ranking of devices and algorithms with respect to the entire measurement window, and is sensitive to vulnerabilities in the underlying high-dimensional geometry of the measurement vectors. The third Computational Blinking, is an architectural mitigation strategy relying on a metric that ranks times during execution of an algorithm in order of vulnerability.

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