UC San Diego

The rapid proliferation of Internet of Things (IoT) devices has revolutionized the technological landscape, permeating various domains and significantly impacting how we interact with the digital and physical realms. As everyday objects become imbued with the capability to collect, manipulate, and acquire data autonomously. Smart distributed sensor networks are formed and are expected to allow transformative changes in sectors such as healthcare, industrial production, and agriculture by allowing continuous monitoring and data-supported decision-making, improving outcomes and efficiency.The design of these highly advanced sensor nodes presents challenges as they must be extremely power efficient to allow for continuous long-term monitoring with a small battery or energy harvester to ensure unobtrusive form factors. A key component to reducing the power consumption and allowing large-scale deployment of IoT sensors is the use of on-device data processing, which reduces the data-transmission bandwidth, latency, and power consumption. This digital heavy preprocessing drives the system design towards selecting highly integrated system-on-chip (SoC) solutions that rely on the advanced process nodes for highly efficient operation of the digital core in charge of data processing at the sensor nodes. However, these advanced technologies do not scale as well for analog front-ends in charge of acquiring the sensor data as they do for digital signal processing with second-order effects significantly degrading key analog transistor parameters (gain, gate leakage, mismatches, etc.), making the design of high-performance analog circuits increasingly difficult. A lot of research has been dedicated to developing alternative architectures that are more resilient or even benefit from technology scaling. Among these architectures, voltage-controlled oscillator (VCO) based analog-to-digital converters (ADC) leverage digital-friendly ring oscillators to perform signal processing and quantization, providing highly scalable analog-to-digital interfaces. These VCO-based ADCs have been mostly designed for high-speed applications with MHz of bandwidth but have started showing their potential for lower bandwidth sensor nodes thanks to their supply insensitivity, infinite DC gain, and compact area. However, many challenges are associated with designing high dynamic range (DR) ADCs using VCO-based integrators as they have limited intrinsic linearity and require a large oversampling ratio due to being limited to 1st-order noise shaping. This dissertation presents several innovations at the circuit and architecture level that can increase the noise-shaping order of VCO-based ADCs and achieve outstanding linearity. These techniques were integrated into two prototype chips: 1) an ADC for the direct-digitization of biopotential signals and 2) a purpose sensor front-end ADC for ultra-low-power IoT nodes. The first prototype is intended to be used for wearable continuous health monitoring. It was designed to interface directly with high-impedance recording electrodes and provide a wide dynamic range and linearity to absorb motion artifacts and correct them in the digital domain. The prototype ADC achieves 2nd-order noise-shaping with high linearity and power efficiency using a novel Gated-inverted-ring-oscillator(GIIRO)-based time-to-digital converter and a multi-quantizer scheme. The ADC achieves a dynamic range greater than 90 dB and above 110 dB of linearity while consuming only 5.4 µW of power. This corresponds to a Schreier Figure of Merit (FoM) of 174.7 dB, which was state-of-the-art for VCO-based ADCs at the time of publication. The second prototype was developed by building upon the feedforwarding techniques commonly used in the standard voltage domain ADC architectures and applying them to capacitively coupled VCO-based ADCs. Using the pseudo-virtual ground (PVG) at the input of the VCO integrator and feeding it further down the loop, we showed that high linearity and higher-order noise-shaping shaping could be achieved extremely power-efficiently. The prototype achieved 3rd-order noise-shaping with a 92.1 dB SNDR and a peak linearity of 123 dB while consuming only 4.4 µW. This led to a Schreier FoM of 179.6 dB, indicating how efficient the proposed structure is and showing comparable performance to standard voltage domain architectures. These VCO-based ADCs have been mostly designed for high-speed applications with MHz bandwidth but have started showing their potential for lower bandwidth sensor nodes thanks to their supply insensitivity, infinite DC gain, and compact area. However, many challenges are associated with designing high dynamic range (DR) ADCs using VCO-based integrators as they have limited intrinsic linearity and require a large oversampling ratio due to being limited to 1st-order noise shaping.This dissertation presents several innovations at the circuit and architecture level that can increase the noise-shaping order of VCO-based ADC and achieve outstanding linearity. These techniques were integrated into two prototype chips: 1) an ADC for the direct-digitization of biopotential signals and 2) a purpose sensor front-end ADC for ultra-low-power IoT nodes. The first prototype is intended to be used for wearable continuous health monitoring. It was designed to interface directly with high-impedance recording electrodes and provide a wide dynamic range and linearity to absorb motion artifacts and correct them in the digital domain. The prototype ADC achieves 2nd-order noise-shaping with high linearity and power efficiency using a novel GIRO-based time-to-digital converter and a multi-quantizer scheme. The ADC achieves a dynamic range greater than 90 dB and above 110 dB of linearity while consuming only 5.4 μW of power. This corresponds to a Schreier Figure of Merit (FoM) of 174.7 dB, which was state-of-the-art for VCO-based ADCs at the time of publication. The second prototype was developed by building upon the feedforwarding techniques commonly used in the standard voltage domain ADC architectures and applying them to capacitively coupled VCO-based ADCs. Using the pseudo-virtual ground (PVG) at the input of the VCO integrator and feeding it further down the loop, we showed that high linearity and higher-order noise-shaping shaping could be achieved extremely power-efficiently. The prototype achieved 3rd-order noise-shaping with a 92.1 dB SNDR and a peak linearity of 123 dB while consuming only 4.4 μW. This led to a Schreier FoM of 179.6 dB, indicating how efficient the proposed structure is and showing comparable performance to standard voltage domain architectures.