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Spur reduction techniques for fractional-N PLLs

  • Author(s): Wang, Kevin Jia-Nong
  • et al.
Abstract

Fractional-N phase locked loops (PLL) are widely used in modern communication systems to synthesize a highly pure frequency from a lower reference frequency. Stringent requirements are often placed on the spectral purity of the synthesized frequency so that overall system-level requirements are met. Unfortunately, spurious tones are inevitable in the output signals of fractional-N PLLs, and in conventional designs they can be attenuated only with design tradeoffs that degrade other aspects of performance. This dissertation presents a PLL that utilizes a successive requantizer in conjunction with an offset current technique to suppress both the fractional and reference spurs. A passive, type-II, sampled loop filter (SLF) is also introduced to mitigate the increased reference spurs that result from the use of an offset current. Chapter 1 describes a phase-noise canceling, fractional-N PLL utilizing the techniques mentioned above. It details the system level and circuit level design and presents measured results. Chapter 2 presents a discrete- time model for a PLL utilizing the passive SLF described in Chapter 1. A mathematical basis for the model is also presented. Chapter 3 describes an integer-N, realigning PLL utilizing a relaxation oscillator and a calibration scheme to suppress the realignment spur. Realignment can suppress the noise of the voltage controlled oscillator (VCO) and hence finds application in systems utilizing non -LC based VCOs. However, implementation challenges exist with regard to the VCO and many previously published designs suffer from a large realignment spur. The use of a relaxation oscillator and the calibration scheme address these two challenges

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