Toward Autonomous Verification Systems
Design verification has been a challenging problem due to the increasing complexity of modern system-on-chip (SoC) designs and it is considered one of the costliest processes in hardware design flow. This dissertation investigates a major labor-intensive task, generating tests to hit a given coverage point, in simulation-based verification, and proposes an autonomous software system capable of completing the task. A key feature of the proposed system is its learning capability -- it can learn from examples provided by human engineers to improve itself. There are three major components in the proposed system: test generation, a knowledge database, and rule learning algorithms. The proposed system is able to retrieve information from the database, use the information to analyze simulation results, and generate new tests based on the analysis. Several machine learning techniques are used in the proposed system. For test generation, a novel method, constrained process discovery, is used to learn a test case generation model from manually developed tests. The test case generation model can create new tests and increase its test generation capability by learning from tests developed by humans. For creating a knowledge database, text mining methods are used to extract important design features from design documents. Experiments showed that the extracted signals can be utilized as observation points to infer important hardware events. Last, a novel rule learning method, VeSC-CoL, is proposed to analyze simulation results. VeSC-CoL can handle extremely imbalanced data, which is common in verification, while traditional rule learning methods cannot.