Mapping of an APNG Encoder to the Grid of Processing Cells Architecture
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Mapping of an APNG Encoder to the Grid of Processing Cells Architecture


Modern processors experience memory contention when the speed of their computationalunits exceeds the rate at which new data is available to be processed. This phenomenon is well known as the memory bottleneck and is a great challenge in computer engineering. In this thesis, a proposed computer architecture using local memory called ”checkerboard architecture” is compared against existing shared memory architectures. Specifically, a well known multimedia application, Animated Portable Network Graphics (APNG) is used to benchmark the performance. APNG is a lossless image compression algorithm which we have parallelized as well as recoded to use small memory buffers. These optimizations en- able implementation on the checkerboard architecture. The specification and modeling of the APNG encoder application and the checkerboard architecture are discussed. Next, the application is mapped to the new architecture and is compared against existing types of ar- chitectures such as existing shared memory processors to confirm the existence of the mem- ory bottleneck and indicate possible solutions. Our experimental results show significant decrease in both execution time and memory contention in the checkerboard architecture compared to single core as well as shared memory processors.

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