Built-in-Self-Test Circuits for Wideband Phased Arrays and Circuits for Millimeter-wave Radiometry and Low-noise Applications
- Author(s): Kanar, Tumay
- Advisor(s): Rebeiz, Gabriel M
- et al.
The thesis presents wide-band built-in self-test circuits (BIST) for phased array systems and high performance circuits for millimeter-wave radiometry and low-noise applications. The 2-15 GHz BIST is designed using a resistive wide-band coupler at the input of each channel and an on-chip oscillator is employed for the test signal and local oscillator generation. An on-chip 8-phase self-correcting I/Q vector receiver and algorithm are introduced for wide-band accuracy. Using the I/Q outputs from 8 different LO phases for one-time calibration, the DC offset, gain and phase imbalance for the system can be determined at each frequency point and eliminated. The BIST can be done at a rate of 1 MHz with greater than 50 dB signal-to-noise-ratio (SNR) and allows for accurate characterization of the phased array by providing relative gain and phase measurements over a wide frequency range. The BIST results agree well with the VNA measurements, and the 2-15 GHz BIST can determine the channel's relative phase and gain error with 3 and 0.3 dB accuracy, respectively. An RMS detector network is also implemented for absolute gain measurements, and the absolute gain is measured using a pair of detectors located at the input and the output ports. The BIST can measure the absolute gain with 0.5 dB accuracy at 2-15 GHz, and this feature can be employed to detect under-performing units in the field for self-healing mechanisms.
Next, a D-band radiometer centered at 136 GHz is presented. The radiometer is realized with a 35 dB gain low-noise amplifier and a detector in the IBM 90 nm SiGe BiCMOS process. The on-chip radiometer results in a measured minimum NEP of 1.4 fW/Hz1/2 and a peak responsivity of 52 MV/W. With a low 1/f corner frequency (<100 Hz) and a noise bandwidth >10 GHz, this system is suitable for high-resolution imaging applications. For an integration time of 3.125 mS, the minimum noise equivalent temperature difference (NETD) is measured to be 0.25K using different independent methods and is the lowest NETD demonstrated in silicon technologies at D-band frequencies.
Finally, X- and K-band low-noise amplifiers (LNA) in a 0.18 μm SiGe BiCMOS process are presented with measured mean noise figure of 1.2 dB and 2.2 dB, respectively. A method of noise match optimization with respect to base inductance in SiGe LNA design with large transistors is proposed and explained in detail. The LNAs result in peak gain of 24.2 and 19 dB at 8.5 and 19.5 GHz and IIP3 of -11 and -4 dBm at 10 and 20 GHz, respectively. To the authors' best knowledge, these results outperform all available CMOS designs and achieve the lowest mean noise figure at X- and K-bands in any SiGe or CMOS process at the time of publication. Another K-band LNA is also implemented in 45 nm IBM CMOS SOI process and results in 2.2 dB mean noise figure with 19 dB peak gain. The details of this design are presented in the appendix.