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Seven Obstacles in the Way of Standard-Compliant Parallel SystemC Simulation

Abstract

© 2016 IEEE. The IEEE 1666-2011 standard defines SystemC based on traditional discrete event simulation (DES) and sequential co-routine semantics, despite explicit parallelism in the model and ample parallel processor cores available in today's host computers. In order to evolve the SystemC standard toward faster parallel DES, substantial hurdles must be overcome. This letter identifies seven obstacles in the standard that stand in the way of efficient parallel SystemC simulation, namely the co-routine semantics, simulator state, lack of thread safety, the role of channels, TLM-2.0, sequential mindset, and temporal decoupling. For each obstacle, we discuss the problem and propose a potential solution toward truly parallel SystemC. This letter to the editor is meant to identify difficulties with IEEE SystemC and stimulate fruitful discussion in the community.

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