Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking
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Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking


Nowadays, the relentless need for increased functionality and speed of ubiquitous electronic and optoelectronic devices with reduced cost, size, and weight call for novel on-chip and off-chip interconnect technologies. Thus, in addition to the continuing overall push for an ever-shrinking pitch size of off-chip interconnections, there are compelling reasons to seek an alternative chip bonding approach enabling simultaneous mechanical, thermal, and electrical interconnections with a much reduced vertical dimension than what can be achieved by the current mainstream bump and bumpless methods.This dissertation explored a new die-attach method used for die-substrate electrical interconnection without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material. A chip bonding method with a concept of “nano-locking” (NL) is proposed: The new method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its successful application for the attachment of high-power GaN based semiconductor dies to its device substrate. In Chapter3, the electrical, thermal, and optical performances of devices enabled by the present NL bonding are evaluated. The resulting bond-line thickness of devices enable by NL bonding approach achieved is shown to be as low as 30 nm, several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance, and a reduced electrical resistance, and thus an improved overall device performance. In Chapter4, the wet high temperature operating life test and thermal cycling test are performed to evaluate the reliability of the packaged devices enabled by the NL bonding method and compared with the conventional Ag-epoxy and AuSn bonding approach. The experimental results help demonstrate the fact that the NL bonding approach helps reduce the risk of interfacial delamination during bonding operation and the chances of commonly observed failure caused by interfacial delamination and the mechanical breakdown can be significantly reduced without adding the conductive metallic fillers. Chapter5 and Chapter6 focused on the study on the influence of bond-line thickness (BLT) and surface morphology on the device performance and reliability. The performances and reliability of the devices enabled by the NL bonding method follows a power-law relationship with the different BLT and different density of surface height distribution and leads to different value of electrical and thermal resistance. The present work opens a new direction for the scalable, reliable and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. In addition, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well.

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