UC Davis

Various types of memory devices have been investigated for the development of next-generation memory technology with high operating speed, high reliability, and low leakage currents. Thyristor Random Access Memory (TRAM) can be one of the most promising candidates. In this work, we demonstrate the memory operation characteristics of TRAM with measurement and simulation results. The results have shown non-volatile characteristics while holding voltage applied. The holding voltage is required voltage condition to keep charges stored in memory. TRAM also has shown high speed switching operation with device PNPN structure. However, the conventional TRAM with two terminal designs has some disadvantages such as short retention time and large leakage currents. Additionally, the PNPN device structure has shown difficulties in controlling the current flows. Therefore, we propose a Three-Terminal TRAM (3T-TRAM) design and compare the device performance with the conventional Two-Terminal TRAM (2T-TRAM). The proposed 3T-TRAM has an additional gate contact to control the currents flow, which makes low leakage currents and high retention characteristics. The optimized design with different doping conditions has been investigated. With the optimized design, we can expect that 3T-TRAM can replace current dynamic random-access memory (DRAM) with excellent performance and be applied as a next-generation high speed computing memory.