Department of Computer Science & Engineering

The embedded market has always been a major source of income to the semiconductor market. As both general purpose and embedded processors are moving towards mobile markets different design criterion are becoming more important. The traditionally performance driven field of processor design now has power issues to deal with. Typically there is a performance requirement, and low power, low cost solutions must be found. In this paper we investigate a software and hardware solution for reducing DRAM power. We propose to mark DRAM rows that have data that will not be read again, and then have the memory controller avoid refreshing those rows. To mark the rows with dead data, we propose adding a new instruction freeNrows to the instruction set architecture, to communicate to the memory controller that N rows starting at the address provided should not be refreshed. If a store ever occurs to a non-refreshed row, then the memory controller will change the status of that row to refresh. For the heap memory, a custom allocation routine will be used to mark DRAM rows as non-refresh, when an object is freed from memory. For global memory, compiler analysis can be used to find global data objects (including large arrays) that have part or all of their object as dead leaving a region of code, and then a freeNrows instruction would be inserted to mark all those DRAM rows as non-refreshed. Our results show that on average 60% of the refreshes issued could be ignored without compromising correctness.

Pre-2018 CSE ID: CS2000-0649