UC Riverside

Reliability has become a more serious design challenge for current nanometer very- large- scale integrated (VLSI) circuits especially as the technology has advanced into 7nm. It was expected that the future chips would show sign of reliability-induced age much faster than the previous generations. Among many reliability effects, electromigration (EM) and time- dependent-dielectric-breakdown (TDDB) induced back-end-of-line (BEOL) reliabil- ity have become major design constraints. EM is a physical phenomenon of the oriented migration of metal (Cu) atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change thus functional failure of the sys- tem. With aggressive technology scaling, EM signoff is becoming more difficult than before using traditional EM analysis approaches. TDDB is caused by formation of a conducting path through the low-k dielectric between metal. It results in a significant leakage increase between interconnects that degrades the circuit performance and causes the chip operation failure. There is still no universal agreement between the proposed TDDB models and the underlying physics of the dielectric breakdown, especially in BEOL interconnects, is still

not completely defined.

This research focuses on developing new physics-based EM and TDDB models and

chip-scale assessment techniques for nanometer VLSI circuits, which overcome the problems existing the traditional analysis approaches and help the reliability sign-off at the design stage. Specifically, first, we have developed physics-based models for estimating the EM- induced stress evolution, void nucleation time, pre- voiding/post-voiding stress evolution accompanying the void motion. Interconnect-tree based analysis method is discussed to account for the inter-dependency between the branches in a tree. Second, we have proposed a novel IR-drop based full-chip EM assessment method to analyze the EM-induced degradation in the power grid networks. This method is further integrated with full-chip thermal and residual stress analysis so that the impact of cross-layout temperature and residual stress distributions can be taken into account. Existing EM models work only for constant temperature and current densities, which cannot reflect practical chip working conditions. We have proposed a new physics-based dynamic compact EM model, which for the first time can accurately model the EM process under time-varying current density and temperature stressing conditions and can predict the transient EM recovery effect in a confined metal wire, which can be further exploited to significantly extend the chip lifetime. Last but not least, we have presented a novel approach, techniques, and flow for the physics-based chip-scale assessment of backend low-k TDDB, where the extracted TDDB lifetime model agrees with the observation obtained from the experimental results. The proposed flow provides a capability to evaluate chip-scale low-k TDDB reliability based on the calculated TTF and can detect most leaking shapes in the layout. It can be further

employed in circuit/system-level reliability aware design optimization.