UC San Diego

In this work we model and implement detailed and large- scale neural and synaptic dynamics in silicon integrated circuits. The aims of this work are to accelerate neuroscience research through analysis by synthesis, and to explore scaleable, hierarchical, sparse event-driven, computing architecture inspired by cortical structure for efficient information processing. In one approach, we implement biophysical Hodgkin-Huxley based membrane dynamics with reconfigurable parameters governing detailed generalized channel kinetics in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform in 0.5[mu]m CMOS chip measuring 3mm x 3mm, and consuming 1.29mW. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. In the same architecture, we implement extended Morris-Lecar dynamics to demonstrate various neural spiking dynamics over a wide range of time scales extending beyond 100ms neglected in typical silicon models of tonic spiking neurons. In a second approach, we design and implement large-scale neural arrays for modeling the spike-based dynamics of cortical neural systems. Towards this end, we present three alternative realizations for highly compact and low- power designs of complex conductance-based models, where each conductance is implemented using a single MOS transistor operating in subthreshold. We present and characterize a mixed-signal VLSI event-driven neural array with 65k two-compartment integrate-and-fire neurons each with four time-multiplexed facilitating conductance-based synapses in a chip measuring 5mm x 5mm in 130nm CMOS and consumes 252[mu]W from 1.5V supply at 5M event/s synaptic input rate resulting in 50pJ/spike power efficiency. The array implements general spike-based neural models with dynamically reconfigurable synaptic connectivity through hierarchical address-event routing of synaptic events. We encode each synaptic event with parameters governing synaptic connectivity, synaptic strength, and axonal delay with additional global configurable parameters that govern neural and synaptic temporal dynamics. We demonstrate this architecture for spike-based event-driven coincidence detection in neural synchrony