UC San Diego

As technology scales, interconnect planning has been widely regarded as one of the most critical factors in determining the system performance and total power consumption. As the result of shrinking dimension, on-chip wires are getting more resistive, and the delay is becoming larger comparing to gate delay. On the other hand, the self capacitance of wires does not scale with feature size, and as wiring density grows, the total coupling capacitance increases, which results in substantial increment of interconnect power consumption. Meanwhile, off-chip interconnect is also becoming a limiting factor for system performance since the growth of chip's I/O bandwidth has been outpaced by the growth of communication. To meet the performance challenge, the per- pin interconnect bandwidth must be further improved with given power budget. For on-chip interconnect, buffer insertion has been adopted to reduce the signal delay. However, the added buffers require extra power consumption and increase routing complexity. In this dissertation, we investigate a set of interconnect performance metrics, optimize the repeated on-chip wires under different design goals and compare the performance metrics of optimum results. The quantitative delay-energy trade-offs for different design goals are demonstrated. Even with repeaters, nominal on-chip global wires still can not keep up with the pace of gate scaling. We propose a high speed signaling scheme using transmission line properties to address the performance issue. The transmission line allows the signal to travel at the speed of light in the medium. The signal toggles as wave instead of enforced electronic charges and thus saves power. However, the inter-symbol interference (ISI) limits the communication bandwidth. We use passive compensation to alleviate the ISI and develop an optimization flow for a given technology and wire dimension. We compare the nominal repeated wires with the transmission lines under different design goals. For off-chip serial links, we propose a set of passive equalization schemes to enhance the performance with low power consumption. We apply the schemes to the CPU-memory links using IBM POWER6 system as a test vehicle. An optimization flow is devised to optimize the parameters of the equalizers. We derive the performance improvement and power consumption of the proposed schemes. We also demonstrate the sensitivities to the variations of RLC parameters and noise