Asynchronous Sampling-Based Hybrid Equalizer Architecture for Wireline Communications
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Asynchronous Sampling-Based Hybrid Equalizer Architecture for Wireline Communications


Video conferencing, data streaming, and web-based business structures are fueling the worldwide demand for Internet usage. The widespread remote work environment induced by the pandemic has increased this demand even further. Internet usage became a new commodity just like electricity or water, and the Internet will continue to be a significant part of our daily lives anytime and anywhere. Wireline communications carry the Internet backbone traffic over copper wires, PCB traces, or optical cables within the data centers and networks utilizing serial link transceivers. Thus, the design of serial link transceivers is an active research area striving for more throughput, higher performance, and lower power/area designs. However, the current wireline architectures utilizing conventional sampling suffer from the limitations of critical circuits, such as track and hold (T/H) circuits and regenerative comparators. In addition, the most advanced process technologies are not providing any significant improvements on the limitations of these sampling circuits. This dissertation describes an alternative equalizer architecture using asynchronous sampling. Applied for the first time to high-speed circuits, asynchronous sampling eliminates the need for T/H and regenerative comparator circuits. The equalizer implementation is a hybrid feed-forward equalizer (H-FFE) utilizing a continuous-time linear equalizer (CTLE) as the main tap and three digital post-cursor taps realized via level-crossing samplers and inverter-based delays. The H-FFE works with event-driven combinational logic based on the incoming data without using synchronous sampling or a high¬-speed CDR. Since the delay of combinational logic is still improving with advanced process nodes, this architecture has the potential for faster designs. Measured test chip results not only serve as the proof of concept but also exhibit comparable performance to recently published design. Fabricated in 40 nm CMOS technology, 4 pJ/bit power efficiency is achieved with a 20 dB Nyquist insertion loss link at a 28.57 Gbps NRZ data rate.

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