UC San Diego

As bulk CMOS is approaching its scaling limit, SOI CMOS is gaining more and more attentions and is considered as a potential candidate for achieving 10-nm CMOS. Fully- depleted SOI MOSFETs have several inherent advantages over bulk MOSFETs-low junction capacitance, no body effect and no need for body doping to confine gate depletion. This dissertation presents a comprehensive, 2-D simulation- based design study on the scaling limit of ultra-thin silicon-on-insulator MOSFETs. Starting with the lateral- field analysis of fully-depleted (FD) SOI MOSFETs, it is shown that the general scale-length model is inapplicable for predicting the minimum scalable channel length when the buried-oxide is very thick. The scaling of FDSOI MOSFETs is independent of the buried-oxide thickness. An empirical prediction equation is developed by approximating the constant contours in a design plane of silicon-film and gate-dielectric thickness. Ultimately, ̃5tSi with a high-k gate dielectric. Other factors such as body doping, substrate biasing, and buried-insulator permittivity and bandgap affecting short-channel scaling of FDSOI are also investigated. Empirical prediction equations are developed for FDSOI devices with body doping and low-k buried-insulators. In principle, the can be improved from ̃5tSi to ̃2tSi by body doping. The can also be reduced 15% shorter from k=3.9 to k=1. Finally, the scaling limit of FDSOI MOSFETs is discussed. From the electrostatic perspective 10-nm FDSOI CMOS requires scaling both high-k gate-dielectric and silicon-film thickness to their limits of ̃2 nm. However, silicon-film thickness cannot below ̃3 nm to avoid severe mobility degradation. The scaling limit of FDSOI MOSFETs with a feasible HfO2 gate dielectric is then projected to be ̃17 nm. 10-nm FDSOI CMOS can be achieved only if there is a breakthrough on thin silicon-film mobility