UCLA

The ever-exploding massive data traffic through both wireless and wireline channels has put critical requirements on the design of high-speed power-efficiency data interface. Serving as the role of bridging the real physical world, of which represented in a continuous form both on the amplitude and time axis, and the computing/controlling digital core operating with quantized measurements in a discrete step-by-step form, the performance matrix of the data interface directly reflects how well the information is preserved after being conveyed from one-domain to the other.

The first part of the dissertation discusses how to effectively mapping the recently emerged Compressive-Sensing theory into real world acquisition hardware implementations and thus provides an alternative solution to potentially improve the power and speed performance of data interfaces which fit in such domain-sparse-signal-oriented processing scheme. Two dual-mode ADC experimental prototypes, one of which is based on self-timed pipeline SAR-BS architecture while the other hybrids voltage-domain SAR-ADC and time-domain locally-readjusted 2D-Vernier TDC, supporting both general purpose Nyquist-Sampling as well as Compressive-Sensing for certain spectral sparse signals, are presented.

The second part focuses on exploring various low-resolution ultra-high-speed DAC implementations for voltage-mode multi-level signaling wireline transmitter design with equalization. A Capacitor-DAC-based approach is proposed due to its inherent advantages on providing linear binary-weighted voltage-domain summing; delivering high swing for capacitive loading; being power efficient and free of driver on-resistance introduced eye-distortion. This architecture is further extended into a pre-distortion-enabled one with independent eye-opening control when the transmitter serves as a baseband modulator for carrier-based communication applications, to effectively correct the non-linear transfer curve of the mixer stage within the RF transmitter. In addition, a C2C-DAC-based architecture is investigated to embed equalization into this pre-distortion-enabled transmitter. To cope with the swing shrink due to the buffer stage for applications requiring channel impedance matching in the Capacitor-DAC-based approach, a R2R-DAC-based transmitter architecture is investigated, which provides compact recursive structural and flexibility to be extended into a multi-tap equalization version.