UC Santa Barbara
III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications
- Author(s): Huang, Cheng-Ying
- Advisor(s): Rodwell, Mark
- et al.
As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal-
oxide-semiconductor ﬁeld-eﬀect transistors (MOSFETs) are promising candidates
for replacing Si-based MOSFETs for future very-large-scale integration (VLSI)
logic applications. III-V InGaAs materials have low electron eﬀective mass and
high electron velocity, allowing higher on-state current at lower VDD and reducing
the switching power consumption. However, III-V InGaAs materials have a nar-
rower band gap and higher permittivity, leading to large band-to-band tunneling
(BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the
channel, and large subthreshold leakage due to worse electrostatic integrity. To
utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high
on-state performance over Si MOSFETs as well as very low leakage current and
low standby power consumption. In this dissertation, we will report InGaAs/InAs
ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in
InGaAs/InAs MOSFETs are reported as described below.
1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match
to InP by molecular beam epitaxy (MBE), and studied the electron transport
in In0.53Ga0.47As/AlAs0.44Sb0.56 heterostructures. The InGaAs channel MOS-
FETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52Al0.48As barriers
were demonstrated, showing signiﬁcant suppression on the back barrier leakage.
2) Ultra-thin channels: We investigated the electron transport in InGaAs and
InAs ultra-thin quantum wells and ultra-thin body MOSFETs (tch∼2-4 nm).
For high performance logic, InAs channels enable higher on-state current, while
for low power logic, InGaAs channels allow lower BTBT leakage current.
3) Source/Drain engineering: We developed raised InGaAs and recessed InP
source/drain spacers. The raised InGaAs source/drain spacers improve electro-
statics, reducing subthreshold leakage, and smooth the electric ﬁeld near drain,
reducing BTBT leakage. With further replacement of raised InGaAs spacers by
recessed, doping-graded InP spacers at high ﬁeld regions, BTBT leakage can be
Using the above-mentioned techniques, record high performance InAs MOS-
FETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated
with Ion = 500 µA/µm at Ioﬀ = 100 nA/µm and VDS =0.5 V, showing the highest
on-state performance among all the III-V MOSFETs and comparable performance
to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP
source/drain spacers were also demonstrated with minimum Ioﬀ = 60 pA/µm at
30 nm-Lg , and Ion = 150 µA/µm at Ioﬀ = 1 nA/µm and VDS =0.5 V. This re-
cessed InP source/drain spacer technique improves device scalability and enables
III-V MOSFETs for low standby power logic applications. Furthermore, ultra-
thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high
yield and high transconductance gm ∼2.0 mS/µm at 20 nm-Lg and VDS =0.5 V.
With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown max-
imum Ion/Ioﬀ ratio ∼8.3×10 5 , conﬁrming that III-V MOSFETs are scalable to
sub-10-nm technology nodes.